Big data analytics in the spotlight at the Ansys’ IDEAS event

Designers of some of today’s most complex chips shared their experiences in a virtual event organized by Ansys on September 23^rd and 24^th. Called IDEAS (Innovative Designs Enabled by Ansys Semiconductor), the web-hosted conference focused on the new multiphysics simulation challenges posed by advanced technology nodes as well as by 3D ICs and chiplet-based designs. The event was used by Ansys to reiterate its approach to simulation and to highlight some of its newest solutions, such as the ones based on the SeaScape big data analytics platform.

A host of new interdependent problems

Let’s briefly recap some of the new problems posed by advanced technology nodes, with the help of Ansys’ white papers. As geometries have shrunk, operating voltage has also scaled down, but threshold voltages of transistors have not scaled proportionately. This has led to an increased sensitivity to voltage drop (IR), and specifically to dynamic voltage drop, which can cause changes in transistor delays and clock jitter. Small geometries also boost the stress effect of high electric fields across the dielectric, resulting in worse aging behavior due to negative bias temperature instability (NBTI).

Besides scaling, the move from planar FETs to FinFETs also introduced new problems by limiting the thermal conduction pathway from the fin structure to the silicon substrate. The combination of these new problems with the ever-increasing transistor count make traditional solutions inadequate. Margining and overdesigning – common solutions for these problems at older technology nodes – would today prevent chips from reaching the best possible PPA results, thus offsetting the benefits of advanced nodes, Margining and overdesigning may also introduce additional issues: for example, using wider metals and more vias to solve electromigration violations leads to poor routability.

On the other hand, the traditional siloed approach to verification is also inadequate for advanced nodes, not only because of the amount of time spent on many independent verification steps, but also because most of the new problems are interdependent and should be simulated together. Similar issues also affect the interdependencies between die, package and system design – as well as the challenges posed by stacked die architectures, which Ansys’ VP and Chief Strategist Vic Kulkarni described in his opening keynote as “a multiphysics nightmare.” Ansys’ response to these new problems is the adoption of big data analytics, allowing to simultaneously take into account all the data available from multiple domains: simulation, timing, layout, power, package design and board constraints.

Sixteen real case presentations

The IDEAS event offered sixteen real case presentations on three parallel tracks, focusing on four main areas: voltage variability & timing; RTL-driven power efficiency & IR sign-off coverage; power integrity signoff for complex SoCs; 3D-IC electrothermal & electromagnetics. These real case presentations were given by Ansys users who develop very complex chips: Intel, Nvidia, Qualcomm, Broadcom, MediaTek, STMicroelectronics, Samsung, Alphawave, Synaptics, Google, HP Enterprise, Xilinx. Here we can only briefly mention some of these presentations as examples.

Google described a methodology to analyze clock jitter to improve PPA, using Ansys’ RedHawk-SC to simulate dynamic voltage drop for several clock cycles and capture the voltage stats on every single transition on each clock instance. This voltage data was then passed to Ansys’ Clock-FX, to calculate the variation of cell delay due to the dynamic voltage drop. This flow enabled the design team to reduce the pessimism from earlier simplistic models, and to pinpoint the clock instances that were the highest contributors of jitter and perform specific fixes to reduce it. Minimizing overdesign due to margin-based approach was also the goal of a timing closure methodology presented by STMicroelectronics, through fast transistor-accurate analysis to rapidly identify the real violations, reducing days of ECO down to hours. Nvidia described a methodology for IR-aware timing sign-off based on Ansys’ PathFX, combining Spice-level accuracy (correlation within 1%) with reasonable runtime.

The methodology described by Samsung concerns evaluation of PDN right after powerplan by generating missing data in heuristic way. This methodology can predict IR drop at early stage within 10% difference in average compared to sign-off result. Intel presented a modelling methodology integrated with Intel Docea Power Analytics (IDPA) that utilizes the estimates provided by Ansys’ PowerArtist (and later in the design lifecycle, with higher accuracy, by Synopsys PTPX) to extrapolate the potential power impact of a new design feature before it is implemented in RTL.

Broadcom presented an Early Predictive Analysis method for the detection of power grid weaknesses using SeaScape big data elastic compute platform, with the addition of RedHawk-SC’s latest Power Profiling  feature to identify instantaneous peak current issues which might otherwise be masked by the traditional method of worst case switching based FSDB cycle selection. This feature can profile chip level timing annotated gate FSDB of several milliseconds duration within a reasonable runtime and memory capacity. Synaptics discussed its simplified IR/EM flow, which avoids the need for domain experts.

Keynotes: from Cerebras’s next wafer scale chip to Ansys’ future AI-based tools

The agenda of the IDEAS event was complemented by two virtual roundtables and nine keynote presentations given by industry leaders from US Air Force, ARM, Cerebras, D-Wave, Ericsson, Stanford University, TSMC, and, of course, Ansys. Again, here we can only briefly quote some of the keynotes as examples. Suk Lee from TSMC delved into details of the 3D IC simulations – based on Ansys tools – that help the Taiwanese foundry to offer its advanced packaging technologies, such as CoWos. Dhiraj Mallick from Cerebras shared a sneak peek of the company’s next Wafer Scale Engine AI accelerator, a 2.6 trillion transistor device featuring 850,000 cores, manufactured in TSMC’s 7-nanometer process; power network signoff for the gigantic chip was achieved using Ansys’ RedHawk-SC, which was able to run on the public cloud.

In his closing keynote, Ansys’ CTO Prith Banerjee discussed the future benefits of using Artificial Intelligence in engineering simulation. As an example, it will be possible to train a neural network to perform a thermal solver simulation by using data from a small tile within the chip; then, moving the tile across the chip, full coverage will be achieved in a short time. According to Banerjee, AI can speed up engineering simulation by several orders of magnitude, and Ansys is already exploring these future capabilities.

Ansys experts’ contribution

Ansys experts of course also played a role in the event, by giving presentations on specific application topics such as side channel leakage vulnerability, data integrity in 5G systems, autonomous vehicles, cloud computing, reliability challenges in advanced packaging, and on specific Ansys products. Mentor and Synopsys also participated, with presentations on power analysis and the “shift left” approach respectively. Concerning the collaboration with these major EDA vendors, it is worth reminding that Ansys describes itself as the enabler of an additional design flow that is ‘perpendicular’ to the main digital design flow, like the wings of an airplane in respect to the fuselage.

Video recording of all the presentations from the IDEAS event should be available on-demand soon from the Ansys website.

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