The 3-nanometer node is approaching, with foundries and EDA vendors preparing to address the future demanding processes. And while “downscaling” is still a key word in chipmaking, “upscaling” is becoming an increasingly important term in video consumption, designating the conversion of old low-definition video content into HDTV or even 4K. Artificial intelligence can help in this seemingly miraculous task. Completing this week’s roundup, we continue to monitor the Silicon Valley tech environment – beyond chips – with a quick look at some mobility-related startups.

TSMC’s roadmap: from N5 to N3

From August 24th to 26th, TSMC held its 2020 Technology Symposium and Open Innovation Platform (OIP) Ecosystem Forum, this year in a virtual format. On this occasion, the Taiwanese foundry provided an overview of its recent achievements and some insights on its roadmap. TSMC’s 5 nanometer N5 technology entered volume production this year, providing a 15% performance gain or a 30% power reduction, and up to 80% logic density gain over the preceding N7 technology. Building on the original N5, the company plans to ramp an enhanced N5P version in 2021, offering an additional 5% speed gain and 10% power improvement. TSMC also provided a preview of the latest member of the 5nm family – the N4 process. N4 is expected to offer further PPA improvements with reduced mask layers, while leveraging the 5nm design ecosystem. The N4 process is scheduled to start risk production in fourth quarter of 2021, with volume production in 2022. As for the next node, TSMC claimed to be “on track” with the development of its N3 process, expected to offer up to 15% performance gain, up to 30% power reduction, and a logic density gain up to 70% over N5, also thanks to “architectural innovations”. Major EDA vendors are already preparing to support N3: the achievement of TSMC certification for this future process node has recently been announced by Ansys, Cadence and Synopsys.
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