EDACafe Editorial Roberto Frazzoli
Roberto Frazzoli is a contributing editor to EDACafe. His interests as a technology journalist focus on the semiconductor ecosystem in all its aspects. Roberto started covering electronics in 1987. His weekly contribution to EDACafe started in early 2019. Mobileye’s approach to AV safety; new Arm IP; security-aware EDA tools; backscatteringMay 29th, 2020 by Roberto Frazzoli
Geopolitical tensions keep on influencing the semiconductor industry. Huawei is reportedly trying to convince Samsung and TSMC to build an advanced chip fab without using U.S. equipment; and former Risc-V Foundation – now called “Risc-V International” – has recently incorporated in Switzerland, a move preannounced by Chief Executive Calista Redmond in this interview. But now, back to technology. Deploying autonomous vehicles at scale will require systems redundancies A recent blog post from Amnon Shashua, CEO of Mobileye, provides several important concepts about the future of autonomous vehicles and his company’s strategy. The key point stressed by Shashua is that “safety must dictate the software and hardware architecture in ways that are not obvious.” Mobileye has already addressed the safety issues linked to the AV decision-making process: the possibility of uncareful driving has been ruled out by clarifying, in a formal manner, what it means to be “careful” (e.g. when merging into traffic); and the need to make predictions about behaviors of other road users has also been ruled out, by always assuming the worst-case scenario. This approach is also being used as a basis for the new IEEE 2846 standard. Having fixed the decision-making process, the only other possible cause of accidents is a glitch in the perception system, whose minimum MTBF requirement depends on the maximum acceptable accident frequency. This is where scale comes into play, as the absolute number of accidents involving autonomous vehicles obviously depends on how many of them are circulating on the roads. In the example provided by Shashua, a fleet of 100,000 robotic shuttles, achieving a maximum frequency of one accident every quarter would require a perception system with an MTBF of 50 million hours of driving – one thousand times better than the error rate of a human driver. In Mobileye’s view, such an ambitious MTBF can only be obtained by introducing system redundancies, as opposed to sensor redundancies within the system. This means equipping the vehicle with two independent and different perception systems: one based on cameras only, and the other on radars/lidars only. The probability of both systems failing at the same time is extremely low. This is why Mobileye is not pursuing the sensor fusion approach; instead, the company has developed a camera-only perception system. Which, by the way, works very well, as shown by this new 40-minute unedited video shot in Jerusalem. New Arm processor IP On May 26 Arm announced four new IP mostly targeting 5G mobile applications, offering significant advances over corresponding previous Arm processors. Cortex-A78 is a CPU for smartphones and other mobile devices, offering a 20% increase in sustained performance over Cortex-A77-based devices within a 1-watt power budget. Cortex-X1 – the most powerful Cortex CPU to date, with a 30% peak performance increase over Cortex-A77 – is the first CPU from the new Cortex-X Custom Program, which allows for customization and differentiation beyond the traditional roadmap of Arm Cortex products. Mali-G78 GPU will deliver a 25% increase in graphics performance relative to Mali-G77, with support for up to 24 cores. Ethos-N78 neural processing unit (NPU) delivers greater on-device ML capabilities and up to 25% more performance efficiency compared to previous Ethos-N77 NPU. Both Synopsys and Cadence are already providing support for the above-mentioned new Arm IP. Synopsys has enabled tapeouts of optimized system-on-chips for early adopters of Cortex-A78, Cortex-X1 and Mali-G78. Synopsys support includes QuickStart Implementation Kits (QIKs) available today. Cadence is supporting Cortex-A78 and Cortex-X1 with a digital full flow Rapid Adoption Kit (RAK); in addition, the Cadence Verification Suite and its engines have been optimized for the creation of designs based on these two new CPUs. DARPA appoints research teams to develop security-aware EDA tools Moving from PPA to PPAS – where S stands for security – when exploring trade-offs or setting design constrains for a new SoC. The goal of DARPA’s AISS program (Automatic Implementation of Secure Silicon) could be described this way, even though the DoD agency uses a different acronym (PASS, meaning Power, Area, Speed, and Security). The AISS program aims at providing SoC designers with new EDA tools that will allow them to specify security constraints, which will then be automatically satisfied by generating the optimal implementation. These future “security-aware EDA tools” will combine an advanced security engine developed within the AISS program, with commercial off-the-shelf IP from Synopsys, Arm, and UltraSoc. DARPA has recently announced the two research teams selected to develop this initiative: one includes Synopsys, Arm, Boeing, Florida Institute for Cybersecurity Research at the University of Florida, Texas A&M University, UltraSoC, and University of California, San Diego; while the members of the other team are Northrop Grumman, IBM, University of Arkansas, and University of Florida. AISS addresses four fundamental silicon security vulnerabilities: side channel attacks, hardware Trojans, reverse engineering, and supply chain attacks (such as counterfeiting, recycling, re-marking, cloning, and over-production). Backscattering startup gets seed financing Transmitting IoT data by “hitchhiking” existing RF signals generated by wireless devices already present in the environment: backscattering could be described this way. This technology is moving from academic research – with works such as the one from the University of California San Diego, presented at the ISSCC 2020 conference – to real products. HaiLa Technologies, a Canadian semiconductor startup that has recently raised $5 million in seed financing, plans to provide early access to the first Wi-Fi IP core based on its backscatter technology by the end of 2020. This will enable companies to develop the next generation of ultra-low power chipsets for IP over Ethernet over Wi-Fi in the IoT space. HaiLa uses a proprietary backscattering technique which allows modulation of digital sensor data on top of ambient signals of different protocols while maintaining the integrity of the signal to the original specific protocol. According to the company, this ensures compatibility of Haila sensor tags to various existing wireless protocols, resulting in a drastic reduction in deployment costs and risks. One of the technical advisors of Haila is Dinesh Bharadia, a professor at the UC San Diego who co-led the above-mentioned research work. |