Archive for the ‘Uncategorized’ Category
Monday, February 13th, 2017
Please save Monday evening, February 27, during DVCon for an entertaining but informative and inspiring panel discussion with today’s emerging verification leaders. Sponsored by the ESD Alliance and OneSpin Solutions, the discussion will be moderated by the always enthusiastic Jim Hogan who will tease out how they are succeeding in a market where much larger competitors also participate.
We plan to start right after the DVCon Expo Booth Crawl that runs from 5-7pm. We’ll have drinks and snacks and there will be planey of opportunity to network. DVCon will be held at the Doubletree Hotel, San Jose, Calif.
Watch this space for more details on who’s participating in the discussion and the room where it will be held.
Thursday, February 9th, 2017
I’m pleased to be able to announce that Grant Pierce, CEO of Sonics, Inc., was elected by the ESD Alliance Board of Directors to serve as chairman. Grant and I have had the opportunity to work together on several Alliance projects and I welcome the chance to work more closely with him. He is an active board member, whose varied industry experience and well-honed skillset will help us forge ahead.
Grant is quoted in our news release as saying: “It is an honor and a privilege to be named chairman of the ESD Alliance by my peers on the board. This is a great opportunity to help guide the organization through the transformation it began in 2016 to broaden its focus to system issues encompassing hardware, software, and design. My experience at Sonics straddling both the system-on-chip IP hardware and design software businesses should serve as a strong unifying asset in this leadership role on the board.”
Tuesday, January 31st, 2017
Rainy winter weather didn’t deter anyone from the Open Source and the RISC-V processor panel Wednesday, January 18, hosted by the ESD Alliance at the Cadence facility in San Jose, Calif. Well, almost everyone. Rick O’Connor, executive director of the RISC-V Foundation, didn’t make it because a snowstorm closed the airport in Ottawa, Canada. Instead, he dialed in from there and gave the audience an overview of the RISC-V Foundation and was available to answer questions. Ted Speers, a member of the RISC-V Foundation board and head of Product Architecture and Planning for Microsemi’s SoC Group, amiably stepped in as his replacement.
The moderator was Jim Hogan of Vista Ventures, our long-time partner who works with Steve Pollock of AI-Pac on the regularly scheduled series like this one presented by our Emerging Companies Committee. Yunsup Lee, SiFive’s chief technology officer (CTO) and co-designer the RISC-V ISA and the first RISC-V microprocessors, offered a fascinating look at the open sources processor movement.
Friday, December 23rd, 2016
Please plan to join us Wednesday, January 18, for a discussion about Open Source and the RISC-V processor featuring Jim Hogan of Vista Ventures, Rick O’Connor, executive director of the RISC-V Foundation, and Yunsup Lee, SiFive’s chief technology officer (CTO). They will describe the path from inception to the open source RISC-V ecosystem, explore whether an open source architecture is appropriate for IoT processing needs and what that means for startups and innovation.
As you’ll hear them say, the number of IoT designs is growing at an astronomical pace. IoT devices are capable of sensing the real world. They are prevalent at the edge of the internet, communicating with an external host to process that real-world information. While there are advantages in performance and cost in processing the data locally, doing so requires significant processing capability at low-energy utilization. Systems designed with autonomous local intelligence have increased but require a microcontroller that can run software that takes energy. What emerged from the academic community are open source alternatives such as RISC-V from UC Berkeley that’s gained momentum over the last few years.
Friday, December 9th, 2016
Registration opened this week for the Phil Kaufman Award Presentation and Dinner to honor Andrzej Strojwas, chief technologist at PDF Solutions and Keithley professor of Electrical and Computer Engineering at Carnegie Mellon University.
I hope you’ll join us for a celebration that helps us kicks off 2017. The dinner will be held Thursday, January 26, at the Fourth Street Summit Center in San Jose, Calif., where we held the dinner paying tribute to Mentor Graphics’ Wally Rhines in 2015. The evening will begin with a reception and cocktails at 6:30 p.m. The dinner and award presentation will be run from 7:30 p.m. until 9 p.m. We have special entertainment planned that will challenge your senses!
Andrzej is being recognized with the award, presented annually by the ESD Alliance and the IEEE Council on Electronic Design Automation (CEDA), for his pioneering research in the area of design for manufacturing (DFM) in the semiconductor industry.
Reservations are $175 per person for ESD Alliance and IEEE members or $250 per person for non-members. Seating is limited and we can accept R.S.V.P.s until Thursday, January 12. To reserve your seat at the 2016 Phil Kaufman Award Presentation and Dinner, visit our online registration.
Tables of 10 are available if your company be interested in sponsoring the event. Sponsorships will heighten a company’s visibility and brand exposure through positive publicity and promotion, and through signage and the program at the event. By sponsoring the dinner, your company is showing the community that it believes in the vibrancy of our industry and honoring those individuals who created it.
To find out more, visit our sponsorship page or call (408) 287-3322.
Tuesday, November 22nd, 2016
While 2016’s coming to an end, it’s not quite over yet and the month of December will be busy for the ESD Alliance.
Our industry has one brand new event called REUSE 2016 that will take place Thursday, December 1. The ESD Alliance will be there, along with close to 40 other exhibitors.
REUSE 2016 is the first of an annual conference and trade show to bring together the semiconductor IP supply chain and its customers for a full day of everything to do with semiconductor IP. It will be held from 11 a.m. until 8 p.m. at the Computer History Museum in Mountain View, Calif. Admission is free.
I’m moderating a conversation during REUSE with Lucio Lanza, managing director of Lanza techVentures, and Dan Rubin, general partner of Alloy Ventures. We’ll talk about the semiconductor IP market and IoT during the discussion titled, “IoT: Poised to offer huge growth opportunities for the global IP Business.”
Wednesday, November 2nd, 2016
I had the pleasure of attending DVCon Europe in Munich, Germany, in mid-October to give the keynote address at the gala dinner. This was my first visit to the conference and I was impressed. As Oliver Bell of Intel and DVCon’s general chair wrote in his welcome greeting in the program, DVCon Europe is a practical, industry application-oriented conference, focusing on design and verification of electronic systems and integrated circuits. I found that to be absolutely true and then some. According to OneSpin’s Vice President of Marketing Dave Kelf, this year’s promotions chair, the conference attendance increased 20%. Kudos to the Steering Committee.
Monday, October 24th, 2016
October continues to be a busy month. I’m just back from a whirlwind trip to Munich, Germany, for DVCon Europe where I was the keynote speaker at the Wednesday night dinner. Stay tuned for a full report in my next blog post.
Meanwhile, if you’re going to ARM TechCon this week, please stop by the ESD Alliance Booth (#523) where you can learn about our programs and new initiatives and pick up a copy of our quarterly newsletter. The Expo Hall will be open Wednesday and Thursday from 10:30 a.m. until 6:30 p.m. at the Santa Clara Convention Center, Santa Clara, Calif.
Thursday, October 13th, 2016
The ESD Alliance’s Emerging Companies Committee has a great topic, excellent moderator and an impressive group of panelists for the second in our ongoing series of panels on legal issues affecting small and emerging technology companies.
“Legal Steps to Maximize your Exit Value” will be held Tuesday, November 1, from 6 p.m. until 9 p.m. at Cadence’s corporate headquarters in San Jose, Calif. Attendees will learn about key valuation issues and techniques, along with more nuanced positioning strategies to build and lock-in enterprise value on exit transactions.
Wednesday, October 5th, 2016
Many thanks to Peggy Aycinena whose blog post is found above mine for her great profile of this year’s Phil Kaufman Award recipient, Andrzej Strojwas (pronounced Andrey Stroyvas), Keithley professor of Electrical and Computer Engineering at Carnegie Mellon University. If you haven’t read it as yet, I highly recommend it.
Andrzej is being recognized with the award, presented annually by the ESD Alliance and the IEEE Council on Electronic Design Automation (CEDA), for his pioneering research in the area of design for manufacturing (DFM) in the semiconductor industry. The relationship between design and manufacturing has never been more important and Andrzej deserves praise for recognizing early on that DFM needed to be a key element of chip design automation. His work was instrumental in bringing design and manufacturing together in a way that has benefited the semiconductor design and manufacturing communities as well as the broader electronics products markets.
The Phil Kaufman Award Ceremony and Dinner to honor him will be held January 26 at the Fourth Street Summit Center in San Jose, Calif., where we held last year’s dinner paying tribute to Mentor Graphics’ Wally Rhines. Wally was honored for growing the EDA and IC design industries through his efforts as a leading voice of EDA and for pioneering the evolution of IC design to SoC design.