Meet UCLA’s Dr. Jason Cong, 2024 Phil Kaufman Award Recipient

I recently had a chance to have a fascinating and wide-ranging talk with Dr. Jason Cong from UCLA, the 2024 Phil Kaufman Award Recipient, about his contributions to FPGA design automation technology and their widespread industrial impact.

The annual Phil Kaufman Award is given by the Electronic System Design Alliance (ESD Alliance), a SEMI technology community, and the Council on Electronic Design Automation (CEDA) of the Institute of Electrical and Electronics Engineers (IEEE). Honors individuals for their distinguished contributions to the Electronic System Design industry.

Smith: Jason, congratulations on being a Phil Kaufman Award recipient. What was your reaction when you got the news?

Cong: First, I want to thank the ESD Alliance and IEEE CEDA for this tremendous recommendation. A long list of pioneers and thought leaders received this award. I read their papers that started my research career and am honored and humbled to be on the list, including my former Ph.D. advisor Chung Laung (C.L) Liu. I had the pleasure of being a tribute presenter for him in 2011.

I was pleasantly surprised. It also felt wonderful to be recognized not just for me but for multiple generations of students and postdocs who participated in our research programs. I’m glad that we made an impact and recognized through this award.

Smith: What initially drew you into the field of EDA?

Cong: I was interested in math. When I was in high school, I had a campus visit to Peking University in China, invited by its Math Department. I stopped by the Computer Science Department on the way back because I was curious to know how computers worked. It took a while to find it because it was in its nascent stage and in a staff residential building. I met someone who gave me a good introduction about the courses.

It was all new to me –– logic designs, data structures, algorithms. So, I made a last-minute change to go with computer science instead of math. The foundation of Computer Science is discrete mathematics and the textbook was by Professor C. L. Liu at the University of Illinois, Urbana-Champaign (UIUC).

It’s a wonderfully written book and he makes a difficult concept easy to learn. I still recommend it to my students. After the course, I wanted to study with Professor Liu for my Ph.D. It turned out that my academic advisor at Peking University visited UIUC and worked with Professor Liu.  He recommended me. That was the only school that I applied to, and I got it in.

Once I got in, I found out he was interested in going into a more application-oriented after doing discrete mathematics all his career. I hesitated but nevertheless agreed. The first project was three-layer channel routing with Professor Martin Wong, now the president of a major university in Hong Kong. We reduced it to a two-processor scheduling problem and further optimized it using the shortest path computation.

I felt at home after this project, as these are combinatorial optimization techniques I have well studied and am passionate about.

Smith: EDA’s come a long way. What excites you about EDA today?

Cong: If you look at my career, I have two phases. During the first phase, I focused on design automation for hardware designers and circuit designers. In the second phase, I’ve been working on design automation for software programmers. You may wonder why I care about whether software programmers can design circuits or not. It’s due to the end of Dennard Scaling. Programmers can no longer automatically get a performance boost of their programs resulting from higher clock frequency of processors.

Parallelization can help to increase performance if the program is parallelizable. A more important technique is customization where a customized architecture fits the application to deliver the best performance. We wrote a proposal in 2008 to the National Science Foundation entitled “Customizable Domain-Specific Computing,” arguing that every important workload needs a specialized accelerator. Now, it’s a well-accepted concept. The Tensor Processing Unit (TPU) from Google, a customized accelerator for deep learning, is an example.

The GPU is also a customized accelerator originally designed for graph processing now well used for dense linear algebra computation, the core of machine learning. Back in 2008, customization was not a well-accepted concept. I’m glad we took the lead in creating various accelerators for different computational kernels.

Rapid accelerator designs need high-level synthesis, a concept around in 2000s and not commercially successful. We put serious effort into making it robust and optimized to produce RTL circuits competitive to human designs, sometimes exceeding them. After some initial success, we spun off AutoESL in 2006 and acquired by Xilinx in 2011, now part of AMD.

At the time of acquisition, we had to go through due diligence with Xilinx. In addition to internal evaluation, Xilinx o retained Berkeley Design Automation (BDA, now Siemens EDA) to do the evaluation. After the acquisition, I encouraged Xilinx to publish those results in an invited paper in IEEE Transactions on Computer-Aided Designs in 2011, which is now well cited.

That’s one area I continue to be excited about. The latest effort is to make it even easier with the help of deep learning. I’m watching closely the progress in machine learning and collaborating with our faculty at UCLA to apply it to chip design automation. I co-wrote a paper titled “Democratizing Domain-Specific Computing” published in Communications of ACM in January 2023. The goal is to enable more people to do chip design. It should not be black art only for highly trained engineers. We hope to bring chip design to a much wider community.

The second area we are concerned about is the end of Moore’s Law scaling. It’s worthwhile looking at fundamentally different technologies. One we’re looking at is quantum computing. You may know a big part of the quantum industry located in Southern California.  We are actively working on compilation and design automation for quantum computing.

Smith: What motivated you and your students to start AutoESL? What were some of the highlights and lowlights or challenges along the way?

Cong: In fact, AutoESL was my second company. The first company was APlus Design Automation, Inc., started in 1998-1999. It was so named not because I’m a professor and only care about students with an A+ grade. It stands for Advanced Programmable Logic Unified Solution with the goal of optimizing FPGA designs combining logic synthesis and physical design. Our lab was known for the FlowMap algorithm, the first polynomial-time depth-optimal mapping for FPGAs with lookup tables. But just counting the depth is not sufficient for performance optimization.

We incorporated various layout aspects into the logic synthesis process. Eventually, Magma (now Synopsys) acquired APlus because it had the vision to use it for both FPGAs and structured ASICs.

When we started the AutoESL project, we were partially inspired by the Xilinx SoC FPGA design, an FPGA fabric with an IBM PowerPC core in the middle. If an engineer started with Verilog or VHDL to design such an SoC, it would not run on an embedded processor. It was much more natural to start with something like C and partition it such as a part that runs on the embedded processor, and the rest to synthesized into the FPGA fabric using high-level synthesis.

Magma, who acquired my first company, wrote a check as a seed investor for AutoESL. Talking about surprises, our first customer inquiry was actually from an investment bank. I asked why and the answer was the need for super-fast security trading. CPUs were not fast enough. The customer wanted to create a circuit to beat competitors by a fraction of a second to get an order in with a better price.

It is both surprising and encouraging to us to see such algorithm developers looked for ways to go from concept to silicon quickly. Not everyone requires low latency trading, but it taught us there was a larger community interested in circuit designs.

Smith: What attracted you to learn and become a bridge player?

Cong: I did it mainly in college, a great social event to get together with four or eight friends. It’s a good way to communicate because there are times between each game to talk. It also teaches building trust and reasoning with probabilities, because this is a game where players don’t see the cards of others and must collaborate with their partners to maximize the winning chance.

I think building trust and confidence is important. It’s also important to be observant and able to catch all signals from both your partner and your opponents.  It’s a subtle and multidimensional game.

I was never that good, but I still enjoyed it. After college, I didn’t get a chance to practice much. I did a bit at Illinois during my Ph.D. studies, but one needed a good, long-time partner. My partner was in Cambridge, U.K. in a Ph.D. program at that time. I didn’t pick bridge up again until the pandemic when everyone was at home. It really doesn’t matter whether you are in the same country, I connected with my old friends via Zoom to play it via an online platform called Bridge.com. It was enjoyable. We don’t play as often as we should, but it was good to get connected with college friends after several decades.

Smith: We covered a lot of ground here. Do you want to add anything?

Cong: I’m grateful to everyone who participated and contributed in our research programs at UCLA and all the collaborators around the world. I know that many of my former students and lab members will come to the Kaufman Award Ceremony and Banquet November 6, so are many friends and collaborators. I look forward to seeing them and thanking them in person.

Note: The Phil Kaufman Award Ceremony and Banquet honoring Dr. Cong will be held Wednesday, November 6, from 6:30-9:30pm at Hayes Mansion in San Jose, Calif. Registration is found on the ESD Alliance website

About Dr. Jason Cong

Dr. Jason Cong is the Volgenau Chair for Engineering Excellence Professor at the UCLA Computer Science Department, and a former department chair, with joint appointments from the Electrical and Computer Engineering Department. He is the director of the Center for Domain-Specific Computing (CDSC) and the director of VLSI Architecture, Synthesis, and Technology (VAST) Laboratory. Dr. Cong’s research interests include novel architectures and compilation for customizable computing, synthesis of VLSI circuits and systems, and quantum computing.

He has over 500 publications in these areas, including 18 best paper awards, and four papers in the FPGA and Reconfigurable Computing Hall of Fame. He and his former students co-founded AutoESL, which developed the most widely used high-level synthesis tool for FPGAs. The tool was renamed to Vivado HLS and Vitis HLS after Xilinx’s acquisition. Dr. Cong is member of the National Academy of Engineering and the American Academy of Arts and Sciences, and a Fellow of ACM, IEEE, and the National Academy of Inventors. He is recipient of the Semiconductor Industry Association (SIA) University Research Award, the EDAA Achievement Award, and the ISPD Lifetime Achievement Award, and he received the IEEE Robert N. Noyce Medal for “fundamental contributions to electronic design automation and FPGA design methods.”

He received his Bachelor of Science degree in Computer Science from Peking University in Beijing, China, in 1985, and his Master of Science and Ph.D. degrees in Computer Science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively.

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