Any chip design group with a project specification that prioritizes improved energy efficiency and performance may want to learn more about Metis Microsystems, a member of the ESD Alliance, a SEMI Technology Community.

This East Coast startup founded in 2017 develops advanced CMOS Memory and Arithmetic component intellectual property (IP) to improve energy efficiency and performance of processors. Metis’ circuit IP harvests a device’s transient data to alleviate circuit limits on CMOS scaling. Applications for the technology are relevant to semiconductor markets limited by compute performance and energy efficiency.

This heady-sounding technology caught my attention, and I was soon seated across from Azeez Bhavnagarwala, Metis’ founder and CEO, at the recent SEMICON West to learn more.

Smith: You talk about data as a source of power. Can you explain further what this means?

Bhavnagarwala: Computing systems represent information with 1s and 0s where the information token of binary data is commonly present in CMOS chips as electric charge.

A 1 is represented at a circuit node by moving charge from the power grid of the chip to the node, raising its electric potential to the supply voltage of the chip. A 0 is represented at a circuit node by draining away the charge it holds, lowering its electric potential to the reference ground potential of the chip.

In both cases, these circuit nodes holding data serve as a source or a sink of electrostatic energy – an equivalent of a silicon battery across circuit nodes that could become available as a resource to partially power memory and arithmetic components.

Smith: How does harvesting energy from transient data impact power and performance?

Bhavnagarwala: CMOS components can harvest data to improve several chip design metrics. For example, harvested data can more than double component performance while also lowering its total energy consumption, enabling reductions in the energy-delay product of CMOS logic and memory components by as much as an order of magnitude. This is accomplished without requiring changes to operating voltages, the CMOS platform or bitcells and without requiring major changes to the design, verification or test workflows.

Harvested data lowers the energy consumed by a binary switching operation to below the physical limits of CV² imposed in conventional CMOS circuits. Power density constraints that emerged with the end of Dennard scaling are also alleviated by using harvested data, removing some constraints imposed by heat removal limits on logic and memory component performance.

Smith: What is the overhead or cost for introducing circuitry that harvests energy from transient data?

Bhavnagarwala: The area efficiency of the proposed circuit IP is higher than that of conventional circuits commonly used in memory instances. A more relevant question is whether conventional approaches are limiting us already from the overhead and costs from using circuitry developed more than 20 years ago for a different set of applications that required different performance, energy efficiency and cost trade-offs.

MOS device structures and associated manufacturing technologies evolved substantially over the last 20 to 30 years. It is time for CMOS circuit IP to catch up. Circuits originally developed for pagers and Blackberry devices cannot be counted on to deliver the compute demands of artificial intelligence (AI) workloads with the energy efficiency expected of wireless devices.

Smith: What applications or markets would most likely benefit from energy harvesting?

Bhavnagarwala: Advances in AI have created a need for compute performance that is on a much steeper growth trajectory than Moore’s Law and doubles every 3.4 months. Historical constraints on hardware performance imposed by limited energy provisions in wireless devices or by heat removal efficiencies in the data center are relevant to processor roadmaps across a very broad range of applications with increasing AI attach rates.

Foundational CMOS IP can help processors meet their performance and energy efficiency targets. Processor markets range from the internet of things (IoT) to augmented reality/virtual reality (AR/VR), automotive, mobile, industrial and surveillance with on-device embedded intelligence. This is a rapidly evolving trend, with industry leaders expecting to see a 100% AI attach rate by 2025.

About Azeez Bhavnagarwala

Azeez Bhavnagarwala previously worked as a scientist at IBM Research, AMD and ARM. Dr. Bhavnagarwala received his Ph.D. in Electrical Engineering from Georgia Institute of Technology and his undergraduate education in Electrical Engineering at Rensselaer Polytechnic Institute in Troy, New York, and the Swiss Federal Institute of Technology (ETH) in Zurich, Switzerland.