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Archive for March 5th, 2018

Chip Design Verification Community’s Travel to San Jose for DVCon

Monday, March 5th, 2018

DVCon is a yearly gathering of the chip design verification community held at the DoubleTree Hotel in San Jose. I’m certain its organizers and steering committee are pleased with attendance, the program, the exhibit floor and the opportunity for attendees to network. The mood was serious and intent on learning –– after all, chip design verification is a huge and complex problem. Nonetheless, everyone was in great spirits.

According to a post-conference news release: “Overall attendance, including exhibit-only and technical conference attendees, was 836.  Attendance was further enhanced by 241 exhibitor personnel that also had access to the panel sessions and keynote address, for a total of 1,077 participants. ”

The ESD Alliance was there and talked with the enthusiastic and energized community of chip design verification experts and aficionados, including vendors on the exhibit floor. Don’t take my word for it. Instead, check out a few photos of our member companies’ booths and the many of their staffers.


DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IoTPLL

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