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 Bridging the Frontier

Archive for March, 2018

Join the ESD Alliance for a Workshop on Digital Marketing

Thursday, March 29th, 2018

 

Lest you think that the CEO Outlook is our only event in April, let me surprise you with an opportunity to learn from experts on how to apply digital marketing to the electronic system design ecosystem.

Yes, we’re hosting a Digital Marketing Workshop Thursday, April 26, with Nicolas Athanasopoulos, OneSpin’s head of digital strategy, and Dave Kelf, chief marketing officer at Breker. Both companies are corporate members of the ESD Alliance.

Nicolas

Dave

Nicolas and Dave will offer presentations on the best marketing practices for an effective social media strategy. They will advise us on ways to implement a web-based content and lead-nurturing plan with cost-effective and proven digital marketing techniques. It’s a terrific opportunity for CEOs, marketing executives, content creators or anyone else from within our ecosystem to learn about implementing or improving their company’s content marketing strategy.

 

Our speakers neatly broke the workshop into four sections:

  1. Introduction –– Tech marketing in the digital age
  2. Inbound –– A strategic model for digital marketing
  3. Digital Marketing –– Tactics that fit the semiconductor industry
  4. A Digital Marketing Case Study

I encourage you to attend. Dave Kelf is a well-known and respected marketing executive who’s managed to cross the chasm from tried-and-true marketing practices into an experienced digital marketer. Nicolas is a relative newcomer and already made his mark at OneSpin as he drives the digital transformation, reaching the community through multi-channel experiences. Both are willing and eager to share their knowledge.

The Digital Marketing Workshop will be held at SEMI in Milpitas, Calif., beginning with breakfast at 7:30 a.m. It will run from 8:30 a.m. until 12:30 p.m. The cost for the workshop is $30 per person for ESD Alliance member companies, $75 per person for non-members. Seating is limited. Registration information can be found at: http://bit.ly/2pvDqlL

We have a few seats left for the ESD Alliance-hosted CEO Outlook Thursday, April 5, at Cadence Design Systems’ Building 10 in San Jose, Calif. Panelists are Arm’s Simon Segars, Dean Drako of IC Manage, Wally Rhines from Mentor, a Siemens Business, and Sonics’ Grant Pierce. Ed Sperling, editor-in-chief of Semiconductor Engineering, will serve as moderator. Each will present a brief opening statement about the future of the industry that will lead to a discussion about trends and opportunities. An interactive and moderated audience discussion will follow.
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The ESD Alliance CEO Outlook –– A Chance to Network, Compare Notes on Industry Trends

Tuesday, March 20th, 2018

Greetings from Dresden, Germany! I’m attending DATE (Design, Automation & Test in Europe), a lively conference sponsored by the ESD Alliance covering a range of topics related to electronic system design.

A reminder that Thursday, April 5, is the date of the 2018 ESD Alliance-hosted CEO Outlook, a rare chance to hear from C-level executives and an opportunity to compare notes on trends and networking with other attendees. Attendees will be able to talk with panelists to learn their thoughts on the semiconductor design ecosystem before they head to the stage. Panelists are Arm’s Simon Segars, Dean Drako of IC Manage, Wally Rhines from Mentor, a Siemens Business, and Sonics’ Grant Pierce. Ed Sperling, editor-in-chief of Semiconductor Engineering, will serve as moderator. Each of the four panelists will present a brief opening statement about the future of the industry that will lead to a discussion about trends and opportunities. An interactive and moderated audience discussion will follow.
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The Popular CEO Outlook is Back

Monday, March 12th, 2018

The 2018 CEO Outlook is scheduled for April 5 and you are invited to join us!

This year, we welcome back Arm’s Simon Segars and Wally Rhines from Mentor, a Siemens Business, and thank Dean Drako of IC Manage and Sonics’ Grant Pierce for agreeing to participate in the discussion about the semiconductor design ecosystem. Ed Sperling, editor-in-chief of Semiconductor Engineering, genially accepted our invitation again this year to moderate the panel made up four of our directors.
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Chip Design Verification Community’s Travel to San Jose for DVCon

Monday, March 5th, 2018

DVCon is a yearly gathering of the chip design verification community held at the DoubleTree Hotel in San Jose. I’m certain its organizers and steering committee are pleased with attendance, the program, the exhibit floor and the opportunity for attendees to network. The mood was serious and intent on learning –– after all, chip design verification is a huge and complex problem. Nonetheless, everyone was in great spirits.

According to a post-conference news release: “Overall attendance, including exhibit-only and technical conference attendees, was 836.  Attendance was further enhanced by 241 exhibitor personnel that also had access to the panel sessions and keynote address, for a total of 1,077 participants. ”

The ESD Alliance was there and talked with the enthusiastic and energized community of chip design verification experts and aficionados, including vendors on the exhibit floor. Don’t take my word for it. Instead, check out a few photos of our member companies’ booths and the many of their staffers.

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Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL
DAC2018



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