What tools do we have in our FinFET toolbox that can help layout engineers manage the complexity that FinFETs inherently bring?
Well for my money, the best and most powerful tool we have to tackle FinFET complexity is the good old parameterized cell or PCell. PCells are not new, they have been around since the CALMA GDS days and along with Schematic-Driven Layout, have been instrumental in boosting layout productivity, as I have mentioned in my previous posts. PCells have typically been used to generate physical layout of pretty much all the devices needed for custom layout, from resistors to inductors, capacitors and, of course, the transistor. That is still the case for FinFET designs; however the role of the PCell has now been expanded to include the schematic PCell.
So what’s the big deal about a schematic PCell, you might ask? And why didn’t we have them before?
Well, some companies did use schematic PCells, but mainly to generate symbols. With FinFET there are many more reasons that a schematic PCell should be used. It boils down to three things: complexity, aesthetics, and productivity.
