Continuing on the theme of FinFET layout, let’s consider what you have to do for routing. Again drawing on the experience of my layout colleagues who are still ‘in the business’ and dealing with FinFETs, here are a few landmines you will have to deal with.
One particular issue they encounter is that although the base layers have shrunk considerably, the shrink of the routing layers has not kept pace. Each new node has brought us smaller transistors, but the minimum metal pitch has not really changed. This really impacts layout floorplanning because designs that were once dictated by device area are now dictated by the ability to route the required signals. Double-/triple-patterning compounds the issue even further.
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