Custom Layout Insights 
Graham Etchells, Director of Product Marketing at Synopsys
Graham Etchells started in EDA before it was termed EDA. He has held marketing and sales positions at several companies and has been chasing the holy grail of analog/custom layout automation ever since he was a marketing director at Cadence in the mid-1990s. He says past experience indicates we may … More » Custom Compiler In-Design Assistants (Part 2)July 14th, 2016 by Graham Etchells, Director of Product Marketing at Synopsys
Planning which metal shape goes on which color (mask) is key when designing in a FinFET process, especially when propagating connections through the layout hierarchy. In addition, highly matched signals such as complementary clocks must be assigned to the same color, as routes on different masks have different resistances. So how do we ensure we are keeping things in order with respect to the matching of resistance and capacitance? Custom Compiler’s In-Design assistants include a built-in engine that computes resistance of a net from a single source to a single destination or multiple destinations. It is an interactive tool that can be run often during the layout process, has a simple use model and a fast response time. To report the resistance of a net, the layout engineer simply selects the net of interest from either the layout, the design navigator or the schematic. The next step is to invoke the resistance report command which pops up in the electrical report menu. The report type is set to “Resistance” and the source and destination points are entered. The report is run and the results are populated in the Electrical Reporter pane. Total resistance and total length for each source and destination point is shown in the top portion of the pane. Selecting one of the source and destination points reveals more detailed information on the contribution that each individual wire makes to the total resistance and length. Selecting an individual wire in the lower portion of the pane highlights the wire in the physical layout. Armed with this wealth of information, the layout engineer can quickly make changes such that the design meets the electrical specifications. Figure 1 shows the results of running the resistance report.
Figure 1. Resistance report with details of each metal wire by layer Another tab on the Electrical Reporter menu allows the layout engineer to run a similar report for capacitance. Selecting the “Capacitance” tab brings up another set of menu options for running the capacitance report. You simply select the net of interest and run the report. The capacitance for the net is extracted using an integrated version of StarRC and, as with the resistance report, the results are populated into the Electrical Reporter pane. Unlike other engines that require an LVS clean design and an extracted view, StarRC extracts the capacitance values from the layout view. This means the layout can be checked frequently as the design evolves without having to complete the design before reporting capacitances. Figure 2 shows the capacitance report.
Figure 2. Reporting capacitances and highlighting wires in the layout Custom Compiler’s In-Design Assistant for resistance and capacitance reports is a fast, simple-to-use reporting utility that, when used interactively during the layout process, reveals detailed information about a net that can be used to quickly determine whether the design is meeting specifications. The ability to do this on a design that is evolving and may not be LVS-correct saves time vs. having to create an LVS-clean design and then waiting for a batch extraction run to complete. Another In-Design Assistant that layout engineers love! Check out Webisode 3 to see Custom Compiler’s In-Design Assistant resistance and capacitance reporting in action. Or watch the Custom Compiler overview webinar. Tags: capacitance, Custom Compiler, custom layout, EDA, FinFET, In-Design, LVS, metal mask, resistance, StarRC, Synopsys |
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