Custom Compiler Layout Assistants (Part 2)

To all of you who attended DAC last week in Austin, TX–welcome back! I hope you were among the 175+ people who attended the Custom Compiler lunch event on Tuesday, June 7 to hear directly from engineers at GSI Technology, Samsung, STMicroelectronics and Synopsys’ IP group who described how Custom Compiler’s visually-assisted automation improves their productivity for both FinFET and established-node designs. We’ll be posting a videolog of the presentations on the Synopsys web site soon for those who missed the live event.

In the last blog I detailed the Symbolic Editor Layout Assistant and showed how the layout engineer can make simple graphical choices of how the layout needs to look and then have the placement taken care of by a placement engine. In this post I will outline another layout assistant: the Routing Assistant. The routing task is one that absolutely screams out for an automated approach, however past efforts have required a great deal of text-based constraints to get anything near to what you really want.

Custom Compiler’s Routing Assistant is a perfect combination of user guidance and automation. It’s a visually-assisted approach that allows the layout engineer to simply click on the starting point of the route and then drag the cursor in the direction they want the routing to follow. As the cursor moves along, behind the scenes the routing engine searches for connections that it can make. When it finds a connection it automatically taps to the pin without the layout engineer having to enter a mouse click. The user simply guides the router with the mouse and it fills in the routing details automatically.

The router is especially good for routing up arrays of FinFETs. FinFET designs have masses of identical common connections and the router understands that. So as it routes, it clones the connections it has just completed to other parts of the layout. As connections are made in one part of the layout, you see them also appear in other areas of the layout that require an identical hook-up.

Figure 1. Interactive routing with automatic cloning and pin tapping

Figure 1 shows the router connecting up the gates of an interdigitated fully-matched differential pair. The yellow flightline shows the starting point of the route and the current cursor position. The router has automatically tapped to the pins and has cloned the routing to the devices in the rows below.

For FinFET-based designs, the router also ensures that all the routing adheres to the correct coloring rules and metal grids. The fact that you can see the routing appear in real time as you move the cursor gives immediate feedback to the layout engineer as to the style of routing that is being generated and allows them to make changes on-the-fly. The router has some options for the style of connections you want to make, such as a fishbone style for routing in between rows where the connections can tap up or down to the pins, but apart from that there are virtually no constraints to enter, no code to write and layout is done in minutes vs. hours.

This powerful combination of user guidance and automatic routing really delivers on reclaiming the loss in custom layout productivity incurred when adopting a FinFET process.

Check out the Custom Compiler Webisode Series (Webisode #2) to see the Routing Assistant in action.

Or watch the full introductory Custom Compiler webinar.

In the next blog post, we’ll take a look at another layout assistant.

Tags: custom IC design, DAC, EDA, FinFET, layout productivity, routing, routing assistant, symbolic editor, Synopsys

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