So, hopefully, you are now aware of Synopsys’ new Custom Compiler solution tuned for rapid implementation of FinFET custom designs. Custom Compiler features a pioneering visually-assisted automation flow that speeds up custom design tasks from days to hours, reduces iterations and enables reuse–very exciting stuff!

But I want to continue my previous discussion thread to help you get a better understanding of the scope of the challenges inherent in FinFET design (and hopefully avoid some pitfalls).

So, going back to where I left off earlier… PCells for custom layout have been a ‘no brainer’ for decades. They have done all the heavy lifting with respect to generating correct-by-construction layout and have been the most important ‘power’ tool for custom layout engineers. Now however, given the complexity of the FinFET process, they become absolutely vital.

Generating a FinFET device is easy when you have a PCell. When coded correctly, it will automatically generate the device such that the fins are properly spaced on the requisite ‘fin grid’ and that all the rules for Poly width/length, Diffusion width/length, Poly cuts and the like are adhered to. In addition to constructing the device design rule correctly, the PCell will also ensure that the metals in the device are colored correctly and abide by the color-related rules. As you can imagine, there is a lot of stuff going on in a FinFET PCell, but there is more. FinFET PCells have to be ‘smarter than the average PCell’ and they have to be in tune with the layout methodology.
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