Custom Layout Insights 
Graham Etchells, Director of Product Marketing at Synopsys
Graham Etchells started in EDA before it was termed EDA. He has held marketing and sales positions at several companies and has been chasing the holy grail of analog/custom layout automation ever since he was a marketing director at Cadence in the mid-1990s. He says past experience indicates we may … More » Current Solutions for FinFET (Part 1)March 28th, 2016 by Graham Etchells, Director of Product Marketing at Synopsys
What tools do we have in our FinFET toolbox that can help layout engineers manage the complexity that FinFETs inherently bring? Well for my money, the best and most powerful tool we have to tackle FinFET complexity is the good old parameterized cell or PCell. PCells are not new, they have been around since the CALMA GDS days and along with Schematic-Driven Layout, have been instrumental in boosting layout productivity, as I have mentioned in my previous posts. PCells have typically been used to generate physical layout of pretty much all the devices needed for custom layout, from resistors to inductors, capacitors and, of course, the transistor. That is still the case for FinFET designs; however the role of the PCell has now been expanded to include the schematic PCell. So what’s the big deal about a schematic PCell, you might ask? And why didn’t we have them before? Well, some companies did use schematic PCells, but mainly to generate symbols. With FinFET there are many more reasons that a schematic PCell should be used. It boils down to three things: complexity, aesthetics, and productivity.
First off, let’s tackle complexity. Because of the very restricted rules for W and L in the FinFET process, it becomes necessary to create arrays of ‘legal’ transistors and stack them connected in-series and parallel to generate your desired W and L. In effect this means that a single transistor symbol in the schematic can map to tens or even hundreds of transistors in the physical layout as shown in Figure 1.
Figure 1 The nice thing about the schematic PCell is that it will automatically create a sub-circuit of this array, instantiate the symbols and make all the necessary connections for you. Second is aesthetics. A single symbol in the schematic is easy to understand, takes up less room and is easy to see and select. It keeps the top level of the schematic neat and uncluttered. Yes, you could accomplish the same with a sub-circuit one level down in the hierarchy, but what if there are changes required? That brings me to the third point of productivity. Let’s say you need to change either the W or L of a transistor. Well it’s much easier to simply select one schematic symbol and change a parameter and have the PCell regenerate the sub-circuit with the required changes, than it is to have to descend in the hierarchy and edit the sub-circuit to reflect the changes. So in my opinion schematic PCells are pretty much a ‘must have’ for FinFET. PCells for layout have been a ‘no brainer’ for decades. They have done all the heavy lifting with respect to generating correct-by-construction layout and are the most important ‘power’ tools for custom layout engineers. They become vital for FinFET for a whole variety of reasons, not least of which is dealing with ‘fin grids’. But that’s another post. Tags: custom design, FinFET, PCell, Schematic PCell, Synopsys |
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