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Posts Tagged ‘Verilog’

System Verilog “ref” is a nice reference instead of “value”

Thursday, December 30th, 2021

Pass by reference is an interesting and very useful feature in system verilog. Very useful and importatn topic to understand and you might hit this as interview question in your next verification interview. This one is one of the very commonly asked interview question. Lets understand…

To begin, lets understand basic concept for pass by value vs pass by reference. In verilog, method arguments takes as pass by value (this is default). The inputs are copied when the method is called and the outputs are assigned  to relevant outputs when exiting the method.

In system verilog, methods can also have “pass by reference”. In this case, arguments passed by reference are not copied into subroutine area instead, a reference to the original arguments are passed to subroutine. In this case subroutines can access the arguments data via reference.

This is very efficient way of passing arguments like class objects or arrays of objects. Scenario like these where you are dealing with class  objects and arrays of objects, if you use pass by value it would create a consume lot of memory on the stack because it has to copy the values and then use it for subroutine. Another advantage of using pass by reference is, since the caller and the function/tasks shares the same reference, any change done inside function using reference would also be visible to the caller.

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System Verilog UVM Callbacks: Development and Usage

Sunday, January 24th, 2021

What is callback? If you know System Verilog, Easily explainable example is post_randomize() method which allows users to execute logic after an object has been randomized.

Callbacks are pre-defined hooks that allow users to influence a verification environment from outside the environment.

The UVM callbacks allow reusable environments to define our own hooks for our application needs. The main advantage of a callback is the ability to combine multiple extensions that are created by multiple teams into a single testbench.

How to Define Callbacks?

First thing, verification engineer to decide is to an interface to make available. Let’s take an example. Say for example you want to add a callback to modify a data packages after it is randomized. This can be implemented as below:

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