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ASIC with Ankit

Archive for the ‘Object Oriented Programing’ Category

System Verilog “ref” is a nice reference instead of “value”

Thursday, December 30th, 2021

Pass by reference is an interesting and very useful feature in system verilog. Very useful and importatn topic to understand and you might hit this as interview question in your next verification interview. This one is one of the very commonly asked interview question. Lets understand…

To begin, lets understand basic concept for pass by value vs pass by reference. In verilog, method arguments takes as pass by value (this is default). The inputs are copied when the method is called and the outputs are assigned to relevant outputs when exiting the method.

In system verilog, methods can also have “pass by reference”. In this case, arguments passed by reference are not copied into subroutine area instead, a reference to the original arguments are passed to subroutine. In this case subroutines can access the arguments data via reference.

This is very efficient way of passing arguments like class objects or arrays of objects. Scenario like these where you are dealing with class objects and arrays of objects, if you use pass by value it would create a consume lot of memory on the stack because it has to copy the values and then use it for subroutine. Another advantage of using pass by reference is, since the caller and the function/tasks shares the same reference, any change done inside function using reference would also be visible to the caller.

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Tags: #asicverification, systemverilog, UVM, Verilog
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System Verilog UVM Callbacks: Development and Usage

Sunday, January 24th, 2021

What is callback? If you know System Verilog, Easily explainable example is post_randomize() method which allows users to execute logic after an object has been randomized.

Callbacks are pre-defined hooks that allow users to influence a verification environment from outside the environment.

The UVM callbacks allow reusable environments to define our own hooks for our application needs. The main advantage of a callback is the ability to combine multiple extensions that are created by multiple teams into a single testbench.

How to Define Callbacks?

First thing, verification engineer to decide is to an interface to make available. Let’s take an example. Say for example you want to add a callback to modify a data packages after it is randomized. This can be implemented as below:

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Tags: #asicverification, systemverilog, UVM, verification, Verilog
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System Verilog Array Randomization

Sunday, January 24th, 2021

System Verilog has different types of arrays that you can randomize to generate interesting scenario for the test bench you are working on. In SV we mainly have static array ,dynamic array and also queues that you can randomize, Lets deep dive in to each one of them to understand how you can use it with system Verilog:

Static Arrays:

class my_static_array;

rand bit [3.0] my_array [8];

endclass

module my_testbench;

my_static_array my_static_array_obj;

initial begin

my_static_array_obj = new ();

my_static_array_obj.randomize();

$display (“my randomize value =%p”, my_static_array_obj.my_array);

end

endmodule

In above example, we have my_array declared as static array which is declared as rand so that you array will be randomize when you do class object.randomize in your module to generate random value for our static array, You can play around with this example by changing different seed to how it changes the random value w.r.t to different seed.

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Tags: UVM, Verilog
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Class – The Classic Feature – Part II

Saturday, April 12th, 2014

Dear AWA Readers

Here we go with follow up post on ‘Class – The classical feature’ ! In this post I will try to cover different types of classes in brief for better understanding. There are various types of classes that we use in test bench development. The usage of class is depends on the requirements. Let’s understand what different types of classes that we use in system verilog.

Different types of classes:

Basic Class
Abstract Class
Parameterised Class
Nested Class
Typedef Class

Basic Class:

Basic class is covered in my last post, you can refer It from here. (more…)

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“Class” – The Classical feature !!

Thursday, October 31st, 2013

Dear Readers,

Let’s understand the classical feature of System Verilog ‘Class‘. Here I would try to explain on class feature, object properties and methods, object instantiation, class methods polymorphism and constructor concept.

What is class and why is it classical 🙂 Lets understand

Class is a generalization of the data type concept and central to the Object Oriented Programming.
A class is a type that includes data and subroutines like functions and tasks.
The class properties and methods creates a capabilities of some kind of objects.

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Tags: Verilog
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