Archive for the ‘ASIC FPGA Verification’ Category
Thursday, December 30th, 2021
Pass by reference is an interesting and very useful feature in system verilog. Very useful and importatn topic to understand and you might hit this as interview question in your next verification interview. This one is one of the very commonly asked interview question. Lets understand…
To begin, lets understand basic concept for pass by value vs pass by reference. In verilog, method arguments takes as pass by value (this is default). The inputs are copied when the method is called and the outputs are assigned to relevant outputs when exiting the method.
In system verilog, methods can also have “pass by reference”. In this case, arguments passed by reference are not copied into subroutine area instead, a reference to the original arguments are passed to subroutine. In this case subroutines can access the arguments data via reference.
This is very efficient way of passing arguments like class objects or arrays of objects. Scenario like these where you are dealing with class objects and arrays of objects, if you use pass by value it would create a consume lot of memory on the stack because it has to copy the values and then use it for subroutine. Another advantage of using pass by reference is, since the caller and the function/tasks shares the same reference, any change done inside function using reference would also be visible to the caller.
(more…)
Tags: #asicverification, systemverilog, UVM, Verilog
No Comments »
Sunday, January 24th, 2021
What is callback? If you know System Verilog, Easily explainable example is post_randomize() method which allows users to execute logic after an object has been randomized.
Callbacks are pre-defined hooks that allow users to influence a verification environment from outside the environment.
The UVM callbacks allow reusable environments to define our own hooks for our application needs. The main advantage of a callback is the ability to combine multiple extensions that are created by multiple teams into a single testbench.
How to Define Callbacks?
First thing, verification engineer to decide is to an interface to make available. Let’s take an example. Say for example you want to add a callback to modify a data packages after it is randomized. This can be implemented as below:
(more…)
Tags: #asicverification, systemverilog, UVM, verification, Verilog
1 Comment »
Sunday, January 24th, 2021
System Verilog has different types of arrays that you can randomize to generate interesting scenario for the test bench you are working on. In SV we mainly have static array ,dynamic array and also queues that you can randomize, Lets deep dive in to each one of them to understand how you can use it with system Verilog:
Static Arrays:
class my_static_array;
rand bit [3.0] my_array [8];
endclass
module my_testbench;
my_static_array my_static_array_obj;
initial begin
my_static_array_obj = new ();
my_static_array_obj.randomize();
$display (“my randomize value =%p”, my_static_array_obj.my_array);
end
endmodule
In above example, we have my_array declared as static array which is declared as rand so that you array will be randomize when you do class object.randomize in your module to generate random value for our static array, You can play around with this example by changing different seed to how it changes the random value w.r.t to different seed.
(more…)
Tags: UVM, Verilog
1 Comment »
Tuesday, March 26th, 2019
As we all know SV has become so popular in verification industry with its very good features and constructs which helps us verify today’s complex designs. Today, I am going to discuss about SVA binding that we use in test bench for SVA properties.
There are VHDL and Verilog model we use to deal with these days. Mostly verification engineers are not allowed to modified these modules. But still SVA addition to these modules are required and easy to verify lot of RTL functionality. How can you add SVA to these modules?
Here is where system verilog ‘bind’ comes in picture. Generally you create a SVA bind file and instantiate sva module with RTL module.
(more…)
Tags: Verilog
No Comments »
Saturday, April 12th, 2014
Dear AWA Readers
Here we go with follow up post on ‘Class – The classical feature’ ! In this post I will try to cover different types of classes in brief for better understanding. There are various types of classes that we use in test bench development. The usage of class is depends on the requirements. Let’s understand what different types of classes that we use in system verilog.
Different types of classes:
- Basic Class
- Abstract Class
- Parameterised Class
- Nested Class
- Typedef Class
Basic class is covered in my last post, you can refer It from here. (more…)
No Comments »
Thursday, October 31st, 2013
Dear Readers,
Let’s understand the classical feature of System Verilog ‘Class‘. Here I would try to explain on class feature, object properties and methods, object instantiation, class methods polymorphism and constructor concept.
What is class and why is it classical 🙂 Lets understand
- Class is a generalization of the data type concept and central to the Object Oriented Programming.
- A class is a type that includes data and subroutines like functions and tasks.
- The class properties and methods creates a capabilities of some kind of objects.
(more…)
Tags: Verilog
No Comments »
Saturday, May 18th, 2013
Dear Readers,
System Verilog has new data type called ‘queue’ which can grow and shrink. With SV queue, we can easily add and remove elements anywhere that is the reason we say it can shrink and grow as we need. Queues can be used as LIFO (Last In First Out) Buffer or FIFO (First In First Out) type of buffers.
Each element in the queue is identified by an ordinal number that represents its position within the queue, with 0 representing the first element and $ represents the last element.
The size of the queue is variable similar to dynamic array but queue may be empty with zero element and still its a valid data structure.
Lets take a few examples to understand queue operation with different methods we have in system verilog.
(more…)
1 Comment »
Wednesday, May 1st, 2013
Dear Readers,
We have been using standard languages and methodologies for ASIC/FPGA design and Verification activities. We as an engineer must know on history of verification activities. Today we mostly work on verification standard languages like System Verilog. The whole industry is moving to accept this language with few methodologies (RVM, VMM, AVM, OVM, UVM etc…) as their standards for new and existing product development and verification.
Now since we use the industry standard languages like VHLD, Verilog, and System Verilog, we must know and understand history and importance of Verification languages.
Let’s understand how we reached to a System Verilog usage? What are the other different verification languages engineers were using in past few decades? How did they start their usage from Verilog to System Verilog for verification? Let’s go back to history and understand these questions.
(more…)
Tags: Verilog
1 Comment »
Thursday, March 14th, 2013
Dear Reader,
Recently I posted one blog post “System Verilog Final Means Final !”
As we all know final means final in system Verilog, Final block will get called at the end of the simulation before $finish. Now with this understanding we can have few questions. Recently few engineers have asked me some questions and thought answering those questions. Questions asked are listed below
- Is multiple final block is allowed in System Verilog?
- If yes, what will be the execution order in simulation, which final is final?
Here are the answers to this questions :
Multiple final blocks are allowed in system Verilog, you can define multiple final block in your testbench. Some time you might require to use final blocks in different places of environment. Here we need to understand one most important thing on final block is that, final blocks are called at the end of the simulation before $finish. It is like a calling a function which executes in zero simulation time.
(more…)
3 Comments »
Saturday, February 23rd, 2013
Dear Readers,
Today I would like to share some basic things on ‘final’block in System Verilog. This is a newly added feature in System Verilog over Verilog. Final block is good for summery information. You can have summery information printed in log file at the end of simulation.
Final block executes at the end of the simulations without delays. ‘final’ block is like an initial block in SV only difference is that it occurs at the end of the simulations. Final block does not allow delays and time consuming or blocking activities and because of this reason it typically used in display statistical information on simulation result. Final block executes in zero time. Considering this nature of execution it is similar to ‘function’.Function also executes in zero time and does not allow timing related or blocking type of activities.
(more…)
No Comments »
|
