System Verilog Array Randomization

System Verilog has different types of arrays that you can randomize to generate interesting scenario for the test bench you are working on. In SV we mainly have static array ,dynamic array and also queues that you can randomize, Lets deep dive in to each one of them to understand how you can use it with system Verilog:

Static Arrays:

class my_static_array;

   rand bit [3.0] my_array [8];

endclass

module my_testbench;

  my_static_array my_static_array_obj;

  initial begin

     my_static_array_obj = new ();

     my_static_array_obj.randomize();

     $display (“my randomize value =%p”, my_static_array_obj.my_array);

  end

endmodule

In above example, we have my_array declared as static array which is declared as rand so that you array will be randomize when you do class object.randomize in your module to generate random value for our static array, You can play around with this example by changing different seed to how it changes the random value w.r.t to different seed.

Dynamic Array:

As we know, Dynamic arrays are the array for which size will not be pre-determined during the declaration. Dynamic array declaration will have square bracket [ ]. Lest deep dive in to example to better understand its declaration and how you can randomize it:

class my_dynamic_array;

rand bit [7:0] my_array [] //dynamic array

//Adding some constraint to this array so we can constraint array during randomization

constraint c1 {my_array.size >2 ; my_array_size <=10;}

//Constraint each array index value to be equal to index+1

constraint c2 {foreach (my_array[i])

                          my_array[i] = i+1;

                            }

function void print_value ();

  foreach (my_array[i])

     $display(“my array value my_array[%0d] = 0x%0h”, i, my_array[i] );

endfunction

endclass

module my_testbench;

my_dynamic_array my_dynamic_array_obj;

initial begin

   my_dynamic_array_obj = new();  //create a memory for the class object

   my_dynamic_array_obj.randomize();  //randomize class with constraint provided

   my_dynamic_array_obj.print_value (); //calling function from class to print array value

end

endmodule

Try this example and play around by changing constraint for index value, array size and seed to see how it changes the value to create corner scenario.

Queue randomization

We can have a queue declared as rand and then later in test bench you can randomize the queue to create a random value generate from the queue elements, We can constraint and limit the queue size in the constraints. Lets deep dive in to the example to better understand declaration of the queue, how you can limit and constraint the size of the queue and how you can randomize the queue to generate random behavior for your test bench:

class my_queue_c;

rand bit [3:0] my_queue [$] // Queue declaration with rand to randomize it later

//constraint to limit the size of the queue

constraint c1 {my_queue.size() == 5;}

endclass

module my_testbench;

my_queue_c  my_queue_c_obj;

initial begin

   my_queue_c_obj = new ();

    my_queue_c_obj.randomize ();

   //Print values

  $display(“my queue value =%p”,   my_queue_c_obj.my_queue);

end

endmodule

Try this example and play around by changing constraint to change size of the queue and seed to see how it changes the value to create corner scenario.

Hope, this is useful simple example to understand randomization of a

rrays. Stay tuned for more simple but exciting post to learn System Verilog.

Keep reading and keep learning, stay tuned for more simple but exciting learning posts

-ASICWithAnkit

Tags: UVM, Verilog

Categories: ASIC FPGA Verification, Object Oriented Programing, System Verilog

This entry was posted on Sunday, January 24th, 2021 at 10:36 pm. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.