EDACafe: ASIC with Ankit

ASIC with Ankit

Archive for January 24th, 2021

System Verilog UVM Callbacks: Development and Usage

Sunday, January 24th, 2021

What is callback? If you know System Verilog, Easily explainable example is post_randomize() method which allows users to execute logic after an object has been randomized.

Callbacks are pre-defined hooks that allow users to influence a verification environment from outside the environment.

The UVM callbacks allow reusable environments to define our own hooks for our application needs. The main advantage of a callback is the ability to combine multiple extensions that are created by multiple teams into a single testbench.

How to Define Callbacks?

First thing, verification engineer to decide is to an interface to make available. Let’s take an example. Say for example you want to add a callback to modify a data packages after it is randomized. This can be implemented as below:

(more…)

Tags: #asicverification, systemverilog, UVM, verification, Verilog
1 Comment »

System Verilog Array Randomization

Sunday, January 24th, 2021

System Verilog has different types of arrays that you can randomize to generate interesting scenario for the test bench you are working on. In SV we mainly have static array ,dynamic array and also queues that you can randomize, Lets deep dive in to each one of them to understand how you can use it with system Verilog:

Static Arrays:

class my_static_array;

rand bit [3.0] my_array [8];

endclass

module my_testbench;

my_static_array my_static_array_obj;

initial begin

my_static_array_obj = new ();

my_static_array_obj.randomize();

$display (“my randomize value =%p”, my_static_array_obj.my_array);

end

endmodule

In above example, we have my_array declared as static array which is declared as rand so that you array will be randomize when you do class object.randomize in your module to generate random value for our static array, You can play around with this example by changing different seed to how it changes the random value w.r.t to different seed.

(more…)

Tags: UVM, Verilog
1 Comment »