ASIC with Ankit 
Ankit Gopani
Ankit Gopani is Experienced Design Verification Engineer. He has been working in the field of ASIC Design and verification and have worked on various IP, SOC, module and subsystem level verification. Ankit has been in the industry for more than 15 years. He is well-known name in the field of ASIC … More » System Verilog Assertion Binding – SVA BindingMarch 26th, 2019 by Ankit Gopani
As we all know SV has become so popular in verification industry with its very good features and constructs which helps us verify today’s complex designs. Today, I am going to discuss about SVA binding that we use in test bench for SVA properties. There are VHDL and Verilog model we use to deal with these days. Mostly verification engineers are not allowed to modified these modules. But still SVA addition to these modules are required and easy to verify lot of RTL functionality. How can you add SVA to these modules? Here is where system verilog ‘bind’ comes in picture. Generally you create a SVA bind file and instantiate sva module with RTL module.
SVA bind file requires assertions be wrapped in module that includes port declaration, So now lets understand this with a small example to understand basic things on how to use SVA bind :
DUT_Module – Dummy RTL module to understand this example SVA_Module – Dummy SVA module with implemented assertion property TB_Module – Dummy test bench code to see how bind works with module instantiation Here, you could see there is DUT instantiation created DUT_u1 instance of DUT_Module. Now point of interest for us would be, how to bind DUT instance to SVA module. To understand this take a look at line number 50 in image from TB_Module, where you could see ‘bind’ keyword used with DUT_Module module and SVA_Module. This is the place where we are binding DUT module with SVA module. Thus passing DUT signal information to SVA module. With this we could play around with DUT signal and can check assertion properties using DUT signals available through this instantiation. If the assertion module uses the same signal names as the target module, the bind file port declarations are still required but the bind-instantiation can be done using the SystemVerilog .* implicit port connections. If signal names are not exactly matching between target and bind file module then we need to expand the instantiation with respected port names. Hope, this information on SVA binding is useful, stay in touch with me and share your views at ASIC With Ankit Tags: Verilog Categories: ASIC FPGA Verification, System Verilog |
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