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Vincent Thibaut
Vincent Thibaut
Vincent, one of Magillem founders, has spent the last 13 years working with Magillem most advanced customers to build the most complete and comprehensive solution for IP Reuse around IP-XACT IEEE1685. As Chief Strategy Officer at Magillem Vincent is working on bringing the future of SoC integration … More »

Arteris IP Extends IP-XACT to UVM Testbenches

July 1st, 2021 by Vincent Thibaut

IP-XACT is a vendor-neutral intellectual property (IP) exchange, configuration and system-on-chip (SoC) assembly standard for portable generator development. The standard is associated with generating a netlist or testing SystemC. It is not widely connected to SoC verification, but this is starting to change because of the proliferation of complex verification IPs (VIPs). IP-XACT simplifies and standardizes building SoC designs around complex IPs. In principle, it could also help develop elaborate SoC testbenches for VIPs.

Why IP-XACT in Testbench Assembly?

To be clear, the goal here is not to autogenerate the internals of the complex test sequences. However, the IP-XACT platform from Arteris IP does handle register sequences. Instead, view the universal verification methodology (UVM) testbench as part of an assembly of the device under test (DUT), plus many complex VIPs. IP-XACT lends itself nicely to this concept. To be effective, packaging needs several extensions so that configuration can be managed from the IP-XACT level. Testbenches will be challenged to include more and more VIPs as design complexity grows. There are compelling reasons to explore IP-XACT packaging for VIPs.

This Is Not Theory

Many Arteris IP customers have already put this idea into practice. These users have already embraced IP-XACT for IP packaging and assembly that ship with the IPs. Bringing VIPs and testbenches into the fold seems to be a logical consideration.

VIPs come from 3rd parties with lots of complex configuration bells and whistles. With such intricacy, things may go wrong. Adhering to a standard can improve design outcomes. There is a way to handle VIP configuration in UVM, but that adds more complexity. Mistakes can add test and debug overhead, further extending the already stretched schedule. And, of course, multiply that verification for DUT, VIP, sim script, and documentation updates and we have created an unnecessary maintenance hassle. Early adopters are solving these challenges with IP-XACT for VIPs. Today, design teams create packaging but are probably already signaling to Accellera and VIP providers that this needs to change.

What Can This Do for Testbenches?

IP-XACT can bring unification in handling VIPs. But there is more. Teams can integrate Register Abstraction Layer testing through the Arteris IP flow. Reusability in testbenches naturally comes with an IP-XACT database, just as it does in design. Most companies already have methodologies for sharing UVM across design teams. This standard could complement what companies already use and manage testbench build through the same script-based interface or graphical environment the design team uses.

The IP-XACT solution from Arteris IP provides documentation support to generate standards-compliant insets to plug into verification documentation. It is an excellent addition, especially when documentation is needed to ship with the product to satisfy automotive, aerospace, industrial or medical requirements.

Engineers are already automating much of testbench building, either through their own scripts or simulation vendor scripts. It would be nice if that could be done through a vendor-independent interface already based on a standard. Extensions to handle this new domain are not yet standardized but working with a platform already used to standardize such features is a good start. To learn more, visit us at

Category: SOC

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