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 Analog Insights

Archive for July, 2012

STE talks about their mixed-signal verification using CustomSim-VCS and VHDL real number modeling for AMS designs

Tuesday, July 31st, 2012

Verification is getting to be a more and more critical step in today IC designs. As more and more analog designs evolve into mixed-signal ones, verification methodologies and strategies need to be further refined and improved to address new challenges. While the verification of the logic part, mostly implemented in Verilog and VHDL, has gained momentum, the analog part suffers from not being supported by this language. To speed up the verification of the analog part (SPICE, Verilog-A(MS), VHDL-AMS), innovation is needed.

In our previous post, we talked about VerilogAMS, which is one approach. In this post, I wanted to talk about an other approach, Real Number Modeling, and highlight the efficient solution developed co-jointly by ST Ericsson and Synopsys, which is based on Synopsys CustomSim-VCS VHDL- Real Number flow. Using this flow, ST-E was able to  boost simulation performance and increase verification coverage of their most complex AMS chips.

Both flows (VerilogAMS and Real Number Modeling) are fully supported by Synopsys.


Call for Abstracts is now open for DesignCon 2013

Tuesday, July 10th, 2012

As a chair(wo)man for the AMS track at DesignCon (yes I know, you heard it before 🙂 ), I just want to inform you that the call for abstracts is now open for DesignCon 2013:

You have until August 17,2012 to submit your abstract. In order to get innovative content, our AMS technical committee selected a large range of topics representative of actual and upcoming challenges faced by AMS engineers (I have included this list below). You can submit your abstract using the above link.

Feel free to contact me anytime if you have any questions, we look forward to reviewing your abstracts.

You can find some related information to last year tutorial and event at:

I am also working on a tutorial and panel focusing on Mixed Signal Verification, more to come later…



Analog, RF, and Mixed-Signal Design and Verification sample topics

Design & verification methodologies

Simulation algorithms and techniques

Mixed-signal behavioral modeling approaches

Verilog-A, Verilog-AMS, VHDL-AMS, SystemVerilog, SystemC-AMS, etc.

Mixed-domain design and verification solutions

MEMS, electro-optics, mechatronics, etc.

Mixed-domain/mixed-language verification strategies

Analog and RF IP: selection, integration, and modeling

Coverage, metrics, and closure management

Power distribution & management

Yield analysis, Monte Carlo methods, and optimization approaches

On-chip inductors: design and modeling

RLCK extraction: post-layout flows and strategies

Noise analysis and prediction: substrate, spurious, random

Variability effects and statistical analyses

Q&A with ST-Ericsson: Latest ERC flow innovations using CustomSim CCK for optimal verification coverage

Monday, July 2nd, 2012

Circuit design implementation has become increasingly complex in deep submicron technologies. Multiple processor cores, I/Os peripherals, complex analog circuits, and logic are now being implemented onto the same chip. Ensuring product reliability to meet design goals and to achieve good yield has become a crucial step in today design cycle. With complex IP, system integration, and multiple power domains, you need an extremely flexible and powerful EDA solution to tackle those circuit verification demands.

Synopsys CustomSim Circuit Check (CCK) provides this solution:  it helps users to avoid wasted simulation time by finding design and performance problems automatically, reporting potential problems in a circuit before running simulation. You can find more information at

I therefore wanted to give you more insights on Synopsys CCK and how our customers are addressing those challenges.  ST-Ericsson presented at our European SNUG event a very innovative flow they developed in tight collaboration with Synopsys using CCK Dynamic ERC (Electrical Rule Checking) for an optimal verification coverage.


ClioSoft at DAC
TrueCircuits: IoTPLL

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