Archive for the ‘SoC Design and Validation’ Category
Monday, April 20th, 2015
How to use VIPs In Practice
Let’s assume that we are designing a new system on chip (SoC) which contains a processor and memory controller, as well as analog and digital peripherals like Ethernet, USB, 1-Wire and JTAG controllers.
Allow me to describe a typical verification process, and explain why I recommend the use of Verification IPs within the testing process.
Figure 1. Typical verification process
Tuesday, February 24th, 2015
This week, February 22-28, we celebrate National Engineers Week in the US to recognize the contributions to society that engineers make. During this time, there is added emphasis in schools on the importance of learning math, science, and technical skills.
I work with Generation STEAM, a group organized by the SYN Shop MakerSpace and the Henderson district library to create a series of STEM (Science, Technology, Engineering, [Art], and Math) classes that are free to the public. For my part, I’ve had the privilege of teaching a basic electronics class for kids a few Saturdays this year – and it’s been a blast. Our hope is that we are encouraging a few young people to follow the path of engineering.
Thursday, December 11th, 2014
Well folks, last call from Engineer Santa. Aldec’s #12DaysofUsefulGifts giveaway will end this Friday, December 12 at 12pm midnight Pacific Standard Time.[preview_cut]
If you haven’t registered yet, you’ll want to hurry and visit www.aldec.com/survey. There you will take a brief verification survey and be entered to win.
If you’ve been keeping up with us on Twitter and YouTube, you know that we’ve given away some fun prizes already. If you are looking for some practical and useful gift ideas for the holidays, you might want to take a closer look. I’ve already talked about some of these from Days #1-4. We’ve given away more prizes since then and sent them to engineers all over the globe! Here, take a look…
Thursday, December 4th, 2014
Happy Holidays! We’ve made it to Day 4 of Aldec’s #12DaysofUsefulGifts giveaway. If you’ve been keeping up with us on Twitter and YouTube, you know that we’ve given away some fun prizes already. But that’s just the beginning, the prizes will get larger each day until the contest ends on December 12th!
If you are looking for some practical and useful gift ideas for the holidays, take a look at some of the fun prizes we’ve already given away.
To enter Aldec’s #12DaysOfUsefulGifts drawing, visit www.aldec.com/survey. There you will take a brief verification survey and automatically be entered to win. You only need to take the survey once to be eligible for daily drawings from Dec 1st-12th. You can also earn additional chances to win by sharing the contest link and viewing the daily contest video. Follow Aldec on Twitter where we will announce each day’s winner and unveil the next day’s prize. Good luck!
Friday, January 10th, 2014
When I first launched Aldec in 1984, home computers hadn’t quite taken off and innovations such as the compact disk and those oversized, power draining cellphones were still struggling to obtain mass acceptance.
Fast forward 30 years, even those of us in the electronics industry have whiplash from the speed at which technology is advancing and delivering new products. Buyers are more eager to become early adopters of innovative new technology, and smarter, faster tools are required to keep pace.
As a long-time member of the Electronic Design Automation (EDA) community, Aldec has had a front row seat to the technology race and over the years we have celebrated many successes of our own. Here, our product managers reflect on some of our most memorable highlights from 2013.
Wednesday, October 9th, 2013
In the last SCE-MI article, we discussed how SCE-MI macro-based infrastructures can speedup SoC design verification time. In SCE-MI 2.1, Accelera introduced a ‘function-based’ infrastructure which is based on SystemVerilog DPI functionality. The SystemVerilog DPI is an interface which can be used to connect SystemVerilog files with foreign languages (C, C++, SystemC, etc).
Wednesday, September 18th, 2013
Today’s System-on-Chip verification teams are moving up in the levels of abstraction to increase the degree of coverage in the system design. As designs grow larger, we start to see an increase in test time within our HDL simulations. Engineers can utilize Hardware-Assisted approaches such as simulation acceleration, transaction-level co-emulation, and prototyping to combat the growing simulation times of an RTL simulator. In this article, we’ll dive much deeper into the transaction-level co-emulation methodology.