Krzysztof SzczurKrzysztof joined Aldec in 2001 and was a key member of the team that developed HES-DVM™, Aldec's FPGA-based simulation acceleration and emulation technology. He has worked in the fields of HDL IP-core verification, testbench automation and design verification for DO-254 compliance gaining practical experience and deep understanding of design verification methodologies, emulation and physical prototyping. As Hardware Verification Products Manager, Krzysztof cooperates with key customers and Aldec's R&D to overcome complex design verification challenges using Aldec hardware tools and solutions. Krzysztof graduated as M.Eng. in Electronic Engineering (EE) at the AGH University of Science and Technology in Krakow, Poland.
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Krzysztof SzczurKrzysztof joined Aldec in 2001 and was a key member of the team that developed HES-DVM™, Aldec's FPGA-based simulation acceleration and emulation technology. He has worked in the fields of HDL IP-core verification, testbench automation and design verification for DO-254 compliance gaining
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Emulation in FPGA
November 22nd, 2017 by Krzysztof Szczur
For many years, emulators were available only to verification teams working on the largest projects in companies with deep enough pockets. Due to size rather than capabilities they were called “Big Box” emulators and typically were used in order to recover some of the time lost on RTL simulation. Meanwhile, FPGA technology has been available long enough to mature to the point where FPGA based emulation became available – and I’m not talking here about FPGA prototyping.
“Emulation – Prototyping, aren’t they just synonyms?”
Sure, they are not. The most significant differences between FPGA usage in prototypes and in emulation are shown in table 1.
|
|
Prototyping
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Emulation
|
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Clock frequency
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10-200 MHz
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1-20 MHz
|
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Clock Topology
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Multiple asynchronous sources – limited number of domains
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Derived from emulation core clock – unlimited number of domains
|
|
Speed Limitation
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Fixed,
Determined by Inter-FPGA signal multiplexing
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Adaptive,
Determined by FPGA-to-Host Comms, Inter-FPGA signal multiplexing
|
|
Stimulus Source
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In-System, Real-world IO
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Host,
Connection with simulators, virtual platforms, virtual models and other testbenches
|
|
Signal Capture
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Selected Nodes
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Full Visibility
|
|
Memory Models
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Near-match to physical
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Modelled
|
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Design Setup
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Computer aided but with extensive user’s input and decisions
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Fully automated
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Table 1: Typical differences between FPGA usage in prototyping and emulation
FPGAs are the fastest platform for prototyping, but we can also harness that speed into our verification environment, then we can achieve runtime performance 2x to 5x faster than traditional “big box” emulation systems, and all at a fraction of the cost per gate per MHz.
“FPGAs are way too small for our SoC design, aren’t they?”
In the HES-US-2640 board, Aldec already has the largest capacity single FPGA boards commercially available today. Connecting 4 such boards in a backplane gives you 24 largest Xilinx UltraScale chips in which you can implement 633 Million ASIC Gates and still have 40% of capacity margin to facilitate FPGA Place & Route.
Figure 1: Scalable HES platform for prototyping & emulation
Not all designs need such excessive capacity, especially IoT projects, where the primary requirement is small footprint and energy-safe design. You will find the proper configuration in Aldec HES boards versatile portfolio containing Virtex-7, Virtex UltraScale and Kintex UltraScale based hardware.
For the rest of this article, visit the Aldec Design and Verification Blog.
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Tags: Emulation, FPGA, hes-boards, prototyping
Category: Emulation/Acceleration
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