Demystifying AXI Interconnection for Zynq SoC FPGA

Imagine traveling back in the time to the early human ages. It’s going to be both scary and interesting when you meet a person who probably cannot speak or if they do you won’t be able to understand them. Clearly, communication will not be possible until you find a mutual way to convey your respective meanings/intentions. The same principle applies in the world of electronics as there are various types of interfaces among electronic devices. Therefore, a standard communication protocol eases the transformation of data in a system, especially in a System-on-Chip (SoC) system which consists of different systems.

SoC FPGAs such as Xilinx® Zynq™ establishes the ARM Advanced Microcontroller Bus Architecture (AMBA) as the on-chip interconnection standard to connect and manage the functional blocks within the SoC design. The Advanced eXtensible Interface (AXI) is designed for FPGAs based on AMBA as a protocol for communication between blocks of IP.

Here are some of the important features of an AXI interface:

• It supports burst transactions with only start address issued
• There are different phases for the data and addresses
• Write and read channels are separated which causes the low-cost Direct Memory Access (DMA)
• Transactions can be completed out of order
• Multiple outstanding addresses can be issued

Regarding the nature of the design, there are two types of AXI4 interface which are shown in Fig. 1. Namely, AXI4 memory map (AXI4 or AXI4-lite) and AXI4-stream.

• AXI4: Capable of doing memory map burst transaction up to 256 data transfer cycles per address phase.
• AXI4-Lite: Utilized for the single bit memory map transaction.
• AXI-Stream: There is no address channel and it allows an unlimited burst transaction between the master and slave.

Fig. 1. AXI interconnection flowchart.

AXI transaction channels

The AXI write and read transaction channels are summarized into 5 categories. In the following text I won’t explain all of the signals in each transaction, just the ones I consider most important (for the purpose of this blog). Fig. 2 shows an AXI interconnection IP and its associated ports in the Xilinx Vivado suite design. For the rest of this article, visit the Aldec Design and Verification Blog.

Tags: Accelerator coherency port, ARM, AXI interconnection, AXI Lite, AXI memory map, AXI stream, embedded, FPGA, General purpose interface, High Performance interface, SoC, TySOM, Xilinx, Zynq

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