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Archive for November 14th, 2016

An Easier Path to Faster C with FPGAs

Monday, November 14th, 2016

For most scientists, what is inside a high-performance computing platform is a mystery. All they usually want to know is that a platform will run an advanced algorithm thrown at it. What happens when a subject matter expert creates a powerful model for an algorithm that in turn automatically generates C code that runs too slowly? FPGA experts have created an answer.

More and more, the general-purpose processor found in server-class platforms is yielding to something more optimized for the challenges of high-performance computing (HPC). Advanced algorithms like convolutional neural networks (CNNs), real-time analytics, and high-throughput sensor fusion are quickly overwhelming traditional hardware platforms. In some cases, HPC developers are turning to GPUs as co-processors and deploying parallel programming schemes – but at a massive cost in increased power consumption.

A more promising approach for workload optimization using considerably less power is hardware acceleration using FPGAs. Much as in the early days of FPGAs where they found homes in reconfigurable compute engines for signal processing tasks, technology is coming full circle and the premise is again gaining favor. The challenge with FPGA technology in the HPC community has always been how the scientist with little to no hardware background translates their favorite algorithm into a reconfigurable platform.
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FPGA VHDL Verification – Can we do this faster – with better quality – at no extra cost?

Monday, November 14th, 2016

As I recently shared, UVVM, VHDL’s long-awaited alternative to UVM, promises to be interesting. Later this week, I’ll be joined by Espen Tallaksen, Bitvis Managing Director and Founder for a joint webinar, UVVM – A game changer for FPGA VHDL Verification.

Below, please find Espen Tallaksen’s recent guest blog on the topic that originally appeared on the Aldec Blog.

FPGA VHDL Verification
How can we do this faster and with better quality – at no extra cost?
by Espen Tallaksen, Bitvis Managing Director and Founder

This is actually possible – and with an average efficiency improvement of 20 to 50% for medium to high complexity FPGAs. Less for data path oriented designs and more for control or protocol oriented designs. At no extra cost.

 All that is required is that you do your testbench development the same way you do your design. Every single FPGA designer knows that a good top level design architecture is critical. Most FPGA designers also know that a good microarchitecture is at least as important for module design. It should thus be obvious that a good architecture is also equally important for your testbench, but for some strange reason most testbenches do not have the same good architecture as the design being verified.

Most designers agree that the following are critical for an efficient development of a high quality design module:

–          Overview, Readability, Simplicity

–          Modifiability, Maintainability, Extendibility

–          Debuggability

–          Reusability

So why should testbenches be any different, with on average the same time usage as the actual design?

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ClioSoft at DAC



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