Aldec and NEC reveal HLS shortcut at upcoming SoC Conference

The University of California, Irvine (UCI) is popular for many things, but I recall during my school days that it was distinctly known among students for its underground tunnel network. The official story is that they were simply built to house heating and cooling pipes. Yet, the rumor persists that this complex maze of underground tunnels was constructed decades ago to provide safe passage for faculty members in case of student riots.

I’ll admit I would love to uncover these tunnels someday, unfortunately they have long been sealed off from curiosity seekers. I will, however, be at the UCI campus next week unraveling a different sort of maze for engineers attending the annual International SoC Conference. Aldec is once again a Platinum Sponsor for this popular academic conference, and this year I will be joined by NEC Corporation’s Dr. Wakabayashi to present a technical session:

FPGA+C-based HLS Can Outperform GPGPU (SIMD Processors) from the View Point of Compiler and Architecture  

Thursday, October 24, 2013 – SoC Conference – UCI – Calit2 Building

For the rest of this article, visit the Aldec Design and Verification Blog.

Tags: asic prototyping, high level synthesis, prototyping, SoC, SoC and ASIC Prototyping, Validation, verification

Category: FPGA Design

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