Agnisys invites you to join our Live Webinar:

Register Design – Tips and Tricks in IDesignSpec

Presented by: Nikita Gulliya, Agnisys R&D Engineer

IDesignSpec has become the de-facto solution for register design/verification. It has helped in the industry minimize SoC functional flaws that show up due to changes and errors in the functional specification by employing a golden specification methodology.

Register for a time that is convenient for you.

Thursday, September 19, 2019
3:00PM – 4:00PM CEST

Thursday, September 19, 2019
11:00AM – 12:00PM PDT

IDesignSpec offers a wide-range of features and capabilities for various design use cases and strategies. As requested by many of our users, in this webinar, we will show you several design strategies and tips/tricks used by power-users of IDesignSpec.

We will cover:

• Tool Overview
• Tips and Tricks
  • Building a Hierarchical Specification
  • Customizing the generated RTL
  • Widely-used RTL Properties
  • Parameterization
  • Connecting custom RTL to the auto-generated register block
  • Creating a TCL as a top-level check for limiting access types, register types, field widths
  • Feature-based availability at block, register and field level
• Q & A