In my last post, I mentioned the three products we announced at the virtual Design Automation Conference (DAC) this year: SoC Enterprise™ (SoC-E), Standard Library of IP Generators (SLIP-G™), and IDS NextGen™ (IDS-NG). I’ve already blogged in detail about SOC Enterprise, so for today I’m focusing on SLIP-G. This library is an extension to our product line that leverages our extensive experience in automating registers and sequences to provide more value for our customers.

It’s no surprise to anyone that design reuse plays a big role in today’s huge system-on-chip (SoC) projects. It’s impractical for any team to design and verify many millions of gates from scratch, so IP from different sources helps to make large SoCs feasible with smaller teams and accelerated schedules. Internal reuse from previous projects is almost universal, but over the past 25 years or so commercial IP has grown tremendously in value and importance. Instantiating a well-proven design block saves valuable time and resources while reducing verification effort.
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