Agnisys Automation Review 
Anupam Bakshi
Anupam Bakshi is Chief Executive Officer (CEO) for Agnisys, Inc., the pioneer and industry leader in Golden Executable Specification Solutions™. From his early days at Gateway Design Automation, through to his time at Cadence, PictureTel, and Avid Technology, he has been passionate about … More » AUGER: Celebrating Our UsersFebruary 12th, 2021 by Anupam Bakshi
In my last post, I discussed the importance of partners to the EDA industry in general, and to Agnisys in particular. Partnerships exist because our users demand them. In today’s post I’d like to focus on a group even more vital to us than partners: the users themselves. I’m choosing this topic partly to highlight our very first Agnisys User Group Educational Roundtable (AUGER), coming up in a few weeks and held virtually as has become the norm for events in our current situation. It seems axiomatic that users are important; if we don’t have customers using our products then we don’t have a business. But it goes deeper than that in EDA. As hard as we try to make our products easy to use, EDA tools have high support requirements. We rarely send a license off to a customer and never hear from them again until renewal time. The norm is that our applications engineering (AE) team builds a close relationship with users as they answer questions and provide guidance. Why Users Care about EDA PartnershipsJanuary 26th, 2021 by Anupam Bakshi
Recently, I’ve been thinking about how vital partners are to the EDA industry in general, and for Agnisys in particular. When I thought about writing a blog post on this topic, I asked myself whether this might be of interest to anyone beyond other EDA companies. After some consideration, I realized that who we partner with, and how, and why, is quite important for our users. In fact, when I talk with both prospective and current customers, this is a topic that comes up quite often. So, I decided to give some background on the way that EDA partnerships work and cite a few noteworthy examples. Let me start with why the idea of partnerships exists at all. The reason is simple: users demand that their EDA vendors work together. The reality is that every chip development team uses tools from multiple vendors. No single vendor, not even any of the “Big 3” industry leaders, offers every possible tool and form of IP required for a comprehensive chip design and verification flow. Users need to be able to choose best-in-class tools from different vendors and deploy them together on a single project. However, users do not want to have to integrate and test the tools together all by themselves. A Unified Development Flow for Embedded SystemsDecember 11th, 2020 by Anupam Bakshi
When engineers discuss system-on-chip (SoC) designs, they’re almost always talking about embedded systems with both hardware and software content. In fact, many argue that a chip must contain at least one embedded processor to qualify as an SoC. Embedded systems have many design and verification challenges, and these apply fully to SoCs. The silicon technology really doesn’t matter; embedded FPGA designs can be huge these days and every bit as complex as ASICs or full-custom chips. Tackling the development challenges for these systems requires an automated, unified flow that covers both hardware and software, spanning design, verification, software, and documentation. Read the rest of A Unified Development Flow for Embedded Systems Functional Safety and Security in Embedded SystemsNovember 17th, 2020 by Anupam Bakshi
Electronics in general, and embedded systems in particular, become more critical every day. There is hardly a single aspect of our lives that is not controlled, monitored, or connected by embedded systems. Even adventurers exploring the most remote regions of our planet carry satellite phones for emergency contact. The ever-increasing role of electronics places huge demands for functional safety and security in the chips and systems we design. I’d like to explore these two topics a bit and recommend that you view a webinar that we recorded earlier this year for a deeper dive. Let me start by differentiating the two terms, especially since “safety” and “security” tend to be used almost interchangeably in everyday speech. Functional safety has a specific meaning when applied to electronics and embedded systems: a measure of the system behaving correctly in response to a range of failures. One commonly cited example of such a failure is an alpha particle flipping a memory bit. If this occurs in safety-critical logic, the design must include a mechanism to detect the failure and correct it if possible. Other failure examples include human error, environmental stress, broken connections, and aging effects. Read the rest of Functional Safety and Security in Embedded Systems A Unified Flow for Embedded Systems DevelopmentOctober 28th, 2020 by Anupam Bakshi
Over the last couple of months, I have discussed some key recent additions to the Agnisys solutions for system-on-chip (SoC) automation, including three new products announced at this year’s virtual Design Automation Conference (DAC). These innovations continue our history of building upon our expertise in the automation of register design and verification to encompass many other aspects of embedded systems development. We provide real value to your architects, designers, verification engineers, software developers, technical writers, and chip testers.
The key idea that links all our products and solutions is using an executable specification as the single source of information across all your project teams. From a single specification, you can generate design RTL, complex programming and test sequences, UVM testbench models for simulation, portable stimulus standard (PSS) models, assertions for formal verification, C code for firmware and device driver development, CSV files for automatic test equipment (ATE), and end-user documentation in multiple formats. No duplication of information means no wasted time, money, or resources and no chance for multiple representations to get out of sync as the project evolves. Changes to the specification require only the push of a button to update all generated files. We support a wide range of specification formats, including industry standards such as IP-XACT and SystemRDL, popular tools such as Microsoft Word and Excel, and our own specialized editors. We generate output files in dozens of different formats to support the diverse users in your teams. Read the rest of A Unified Flow for Embedded Systems Development Automatic Handling of Register Clock Domain CrossingsOctober 15th, 2020 by Anupam Bakshi
Register-transfer-level (RTL) code, formal analysis, RTL simulation, and logic synthesis have all raised the abstraction level of electronic design and verification. Today’s designers operate very differently than their predecessors who drew circuit-level schematics and ran only SPICE. However, underneath all this abstraction the physical properties of electronic devices remain unchanged, and these must be considered during design. One well-known example is metastability, which can occur wherever a signal crosses between flip-flops running on asynchronous clocks, known as a clock domain crossing (CDC). The most common example of metastability happens when the output value of a flip-flop on the sending clock changes during the setup and hold time of the clock for the receiving flip-flop. The output of the flip-flop on the receiving clock can take on an indeterminate value that requires some time to settle to a one or zero. If the output of the receiving flip-flop is used immediately, an invalid value may be fed into the downstream logic and produce incorrect results. Unfortunately, there is no way to design a flip-flop that does not have a risk of metastability.
Read the rest of Automatic Handling of Register Clock Domain Crossings AI-Based Sequence Detection for IP and SoC Verification and ValidationSeptember 28th, 2020 by Anupam Bakshi
A couple of years ago at the Design Automation Conference (DAC), as I walked the exhibit floor I was amused by how many EDA vendors had jumped on the marketing bandwagon for artificial intelligence (AI) and machine learning (ML). Many company slogans, booth posters, and demonstrations claimed that AI/ML techniques had been incorporated into their products. Doubtless some of these claims were true, but for certain companies and product categories it was hard to believe. In this post, I’ll discuss a real use of AI/ML technology at Agnisys, already implemented and available to users now. Let’s start by defining a few terms. AI is a broad description referring to any computer program that automatically does something that would traditionally have required human intelligence. AI works at its best by combining large amounts of data with fast, iterative processing and intelligent algorithms. ML is a subset of AI using advanced techniques and models that enable computers to figure out interesting things from the datasets and deliver AI applications. Along with the algorithms, what is most important for AI/ML is the quality and quantity of the data used to train the model for these algorithms. Read the rest of AI-Based Sequence Detection for IP and SoC Verification and Validation Specification-Driven UVM Testbench GenerationSeptember 22nd, 2020 by Anupam Bakshi
In February, we will celebrate the tenth anniversary of Accellera approving the first version of the Universal Verification Methodology (UVM). It’s no exaggeration to say that UVM changed the world of semiconductor verification. It wasn’t the first verification methodology, and not even the first to use SystemVerilog, but it was developed and supported by all major electronic design automation (EDA) vendors. Users could write testbenches using the UVM building-block library and its detailed guidelines, secure in the knowledge that simulators and other tools would handle them properly. UVM focused the diverse set of constructs and powerful capabilities available in SystemVerilog on the specific task of building a reusable verification environment. Object-oriented programming (OOP) support meant that users could extend the building blocks without modifying them. Adherence to the guidelines made verification components reusable “horizontally” across projects and even across companies. Passive components such as monitors and coverage collectors, and even some active interface models, could be reused “vertically” from block to subsystem to system. Read the rest of Specification-Driven UVM Testbench Generation The Next Generation of Register, Sequence, and SoC AutomationAugust 28th, 2020 by Anupam Bakshi
Regular readers of this blog know that Agnisys started as the first company to fully automate the design, verification, and documentation of registers in chip designs. From a single specification, you can generate design RTL, UVM testbench models for simulation, and user documentation for the registers in your design. This saves your development teams weeks of time, especially when the design evolves and register changes can be propagated across the project with a specification update and the simple push of a button. IDesignSpec™ (IDS) remains our best-known and most widely adopted product. We expanded our solutions to include the sequences to access and program your registers with ISequenceSpec™ (ISS). We automatically generate sequences for various types of register behavior, including access to individual fields within registers. This is highly valuable for your chip verification team. We also help your driver and firmware developers by generating C code to access and program the registers in the actual fabricated chip as well as in hardware-software co-simulation and emulation. Like IDS, ISS also generates documentation in several formats. Automating IP Design and VerificationAugust 16th, 2020 by Anupam Bakshi
In my last post, I mentioned the three products we announced at the virtual Design Automation Conference (DAC) this year: SoC Enterprise™ (SoC-E), Standard Library of IP Generators (SLIP-G™), and IDS NextGen™ (IDS-NG). I’ve already blogged in detail about SOC Enterprise, so for today I’m focusing on SLIP-G. This library is an extension to our product line that leverages our extensive experience in automating registers and sequences to provide more value for our customers. It’s no surprise to anyone that design reuse plays a big role in today’s huge system-on-chip (SoC) projects. It’s impractical for any team to design and verify many millions of gates from scratch, so IP from different sources helps to make large SoCs feasible with smaller teams and accelerated schedules. Internal reuse from previous projects is almost universal, but over the past 25 years or so commercial IP has grown tremendously in value and importance. Instantiating a well-proven design block saves valuable time and resources while reducing verification effort. |
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