Archive for the ‘Uncategorized’ Category
Thursday, October 15th, 2020
Register-transfer-level (RTL) code, formal analysis, RTL simulation, and logic synthesis have all raised the abstraction level of electronic design and verification. Today’s designers operate very differently than their predecessors who drew circuit-level schematics and ran only SPICE. However, underneath all this abstraction the physical properties of electronic devices remain unchanged, and these must be considered during design. One well-known example is metastability, which can occur wherever a signal crosses between flip-flops running on asynchronous clocks, known as a clock domain crossing (CDC).
The most common example of metastability happens when the output value of a flip-flop on the sending clock changes during the setup and hold time of the clock for the receiving flip-flop. The output of the flip-flop on the receiving clock can take on an indeterminate value that requires some time to settle to a one or zero. If the output of the receiving flip-flop is used immediately, an invalid value may be fed into the downstream logic and produce incorrect results. Unfortunately, there is no way to design a flip-flop that does not have a risk of metastability.
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Tags: sysremRDL, SystemVerilog, UVM
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Monday, September 28th, 2020
A couple of years ago at the Design Automation Conference (DAC), as I walked the exhibit floor I was amused by how many EDA vendors had jumped on the marketing bandwagon for artificial intelligence (AI) and machine learning (ML). Many company slogans, booth posters, and demonstrations claimed that AI/ML techniques had been incorporated into their products. Doubtless some of these claims were true, but for certain companies and product categories it was hard to believe. In this post, I’ll discuss a real use of AI/ML technology at Agnisys, already implemented and available to users now.
Let’s start by defining a few terms. AI is a broad description referring to any computer program that automatically does something that would traditionally have required human intelligence. AI works at its best by combining large amounts of data with fast, iterative processing and intelligent algorithms. ML is a subset of AI using advanced techniques and models that enable computers to figure out interesting things from the datasets and deliver AI applications. Along with the algorithms, what is most important for AI/ML is the quality and quantity of the data used to train the model for these algorithms.
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Tags: SoC, testbenches
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Tuesday, September 22nd, 2020
In February, we will celebrate the tenth anniversary of Accellera approving the first version of the Universal Verification Methodology (UVM). It’s no exaggeration to say that UVM changed the world of semiconductor verification. It wasn’t the first verification methodology, and not even the first to use SystemVerilog, but it was developed and supported by all major electronic design automation (EDA) vendors. Users could write testbenches using the UVM building-block library and its detailed guidelines, secure in the knowledge that simulators and other tools would handle them properly.
UVM focused the diverse set of constructs and powerful capabilities available in SystemVerilog on the specific task of building a reusable verification environment. Object-oriented programming (OOP) support meant that users could extend the building blocks without modifying them. Adherence to the guidelines made verification components reusable “horizontally” across projects and even across companies. Passive components such as monitors and coverage collectors, and even some active interface models, could be reused “vertically” from block to subsystem to system.
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Tags: testbench, UVM
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Friday, August 28th, 2020
Regular readers of this blog know that Agnisys started as the first company to fully automate the design, verification, and documentation of registers in chip designs. From a single specification, you can generate design RTL, UVM testbench models for simulation, and user documentation for the registers in your design. This saves your development teams weeks of time, especially when the design evolves and register changes can be propagated across the project with a specification update and the simple push of a button. IDesignSpec™ (IDS) remains our best-known and most widely adopted product.
We expanded our solutions to include the sequences to access and program your registers with ISequenceSpec™ (ISS). We automatically generate sequences for various types of register behavior, including access to individual fields within registers. This is highly valuable for your chip verification team. We also help your driver and firmware developers by generating C code to access and program the registers in the actual fabricated chip as well as in hardware-software co-simulation and emulation. Like IDS, ISS also generates documentation in several formats.
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Tags: SystemRDL
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Sunday, August 16th, 2020
In my last post, I mentioned the three products we announced at the virtual Design Automation Conference (DAC) this year: SoC Enterprise™ (SoC-E), Standard Library of IP Generators (SLIP-G™), and IDS NextGen™ (IDS-NG). I’ve already blogged in detail about SOC Enterprise, so for today I’m focusing on SLIP-G. This library is an extension to our product line that leverages our extensive experience in automating registers and sequences to provide more value for our customers.
It’s no surprise to anyone that design reuse plays a big role in today’s huge system-on-chip (SoC) projects. It’s impractical for any team to design and verify many millions of gates from scratch, so IP from different sources helps to make large SoCs feasible with smaller teams and accelerated schedules. Internal reuse from previous projects is almost universal, but over the past 25 years or so commercial IP has grown tremendously in value and importance. Instantiating a well-proven design block saves valuable time and resources while reducing verification effort.
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Tags: Design, Verification
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Saturday, July 18th, 2020
Anyone who’s worked in the EDA industry, and many of its customers, are aware of the annual Design Automation Conference (DAC). This event dates back 57 years, a long time for anything to last in our high-tech world. It’s really two shows in one: a competitive, peer-reviewed technical conference combined with a large vendor exhibition. We have been attending DAC since 2009 and have always found it to be a valuable experience. The technical program is stimulating, we get to check out what other vendors are doing, and we’re able to talk to many customers and prospective customers over the span of just a few days.
Of course, this year is different. As for most other public events and shows, it’s not possible for us to gather together physically at this time. Therefore, DAC 2020 is a virtual event, with the speakers delivering their talks and papers online and the vendors hosting virtual booths. Agnisys is participating as always and we are looking forward to engaging with all of you in a different but still personal way. The virtual booths are configured to enable real-time chats and schedule detailed discussions. We can’t meet face to face or shake hands, but we can listen to your chip design and verification challenges and suggest ways that we can help.
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Tags: dac2020
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Monday, June 29th, 2020
System-on-chip (SoC) projects are, by their very nature, complex and difficult to complete successfully. Specification, architecture, design, and verification are all challenging. This blog post focuses on the challenges faced by designers, driven by the convergence of applications onto a single SoC device. This increases the demand for design functionality and design performance. At the same time, market requirements generate pressure to drive down the cost of design and meet shrinking market windows due to shorter product shelf lives. Every step of the design process has become more difficult, even the seemingly simple task of assembling all the pieces that make up the SoC.
Today’s large chips may contain 500 of more instances of intellectual property (IP), a combination of new designs, reused blocks from previous projects, and licensed commercial IP. If each of these blocks averages 50 ports, then 25,000 connections must be made among them. Making these connections manually is tedious and time-consuming, with a high chance of errors. Meeting cost and schedule goals requires a big increase in the productivity of the SoC design team. Methodology improvements are needed to help accelerate assembly of chips and systems through automation.
The best solution is providing designers flexible, customizable, and configurable IP and subsystem generators along with a tool to automate architectural level SoC assembly and connectivity. The capabilities for such a solution include:
- Creating and editing the design on the fly through scripts or a command line interface
- Generating major subsystems with flexibility to customize or configure
- Automatically adding instances to the design, making connections, restructuring, etc.
- Viewing the resulting schematics for design analysis
- Running design rule checks to endure IP and SoC quality
- Generating appropriate files for design, verification, and software teams
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Tags: SoC, SoCdesign, System-on-chip
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Wednesday, June 17th, 2020
Verifying any large chip design is challenging, but a system-on-chip (SoC) presents additional requirements. By definition, an SoC includes one or more embedded processors, and the code they execute provides a significant portion of the overall functionality. Both the hardware and software must be verified, but they also must be verified together (co-verified) to exercise the full range of intended operation. Although lint checks, formal analysis, and other techniques play a role, the bulk of verification is performed by simulating a testbench compliant with the Universal Verification Methodology (UVM) standard.
Such a testbench environment is a must-have requirement for every SoC project. It provides a means to check the full system before sending the design to the foundry for fabrication. It complements block-level testbenches by verifying that all the connections between the blocks are functioning correctly, that data flows properly around the SoC, and that hardware interrupts and their associated interrupt service routine (ISR) software are working. The testbench can also help the firmware and software engineers write and debug device drivers and applications. Setting up the SoC verification environment can be divided into three steps:
- Creating a testbench compliant with the UVM architecture
- Converting C programs to binary files for the embedded processor(s)
- Synchronizing C programs and UVM tests
The process is similar for any type of embedded processor, but this post focuses on RISC-V since it is a widely used instruction set architecture (ISA) for contemporary SoCs.
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Thursday, May 28th, 2020
A recent blog post noted that today’s RTL design verification (DV) environments are very powerful and very complex. The SystemVerilog-based Universal Verification Methodology (UVM) standard provides most of the key building blocks for the simulation testbenches at the heart of the DV process. The previous post focused on correct-by-construction of UVM testbenches using the DVinsight™ smart editor from Agnisys. This post shows how other solutions from Agnisys can automate the generation of the UVM Register Abstraction Layer (RAL) that provides testbench access to the registers and memories in the design being verified.
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Tags: IDesignSpec, IP-XACT, SystemVerilog, testbench, UVM
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Saturday, May 9th, 2020
Most of us have faced difficulties in our personal and professional lives, and have worked our way through them. But few of us have experience dealing with a challenge as broad and disruptive as the COVID-19 global pandemic. By now, many people know friends and family members who have been sickened or even struck down by this disease. The economic toll is staggering, and recovery will take considerable time. Even with all the coping mechanisms we have developed through dealing with past challenges in our lives, it’s easy to feel overwhelmed.
I think that the best way to handle the stress and uncertainty is to do whatever we can to help our families and community, and those everywhere suffering directly or indirectly from the virus. As an example, a diverse group of companies and institutions recently took an innovative step to establish the Open COVID Pledge. This initiative offers intellectual property (IP) free of charge for the purpose of diagnosing, preventing, containing, and treating COVID-19.
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Tags: COVID Pledge, COVID-19
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