Why Users Care about EDA Partnerships

Recently, I’ve been thinking about how vital partners are to the EDA industry in general, and for Agnisys in particular. When I thought about writing a blog post on this topic, I asked myself whether this might be of interest to anyone beyond other EDA companies. After some consideration, I realized that who we partner with, and how, and why, is quite important for our users. In fact, when I talk with both prospective and current customers, this is a topic that comes up quite often. So, I decided to give some background on the way that EDA partnerships work and cite a few noteworthy examples.

Let me start with why the idea of partnerships exists at all. The reason is simple: users demand that their EDA vendors work together. The reality is that every chip development team uses tools from multiple vendors. No single vendor, not even any of the “Big 3” industry leaders, offers every possible tool and form of IP required for a comprehensive chip design and verification flow. Users need to be able to choose best-in-class tools from different vendors and deploy them together on a single project. However, users do not want to have to integrate and test the tools together all by themselves.

One might think that industry standards guarantee that different tools mesh seamlessly. Standards help a lot, but problems still exist. For example, SystemVerilog is a massively complex language and it is likely that no one supports 100% of it. There are many subtle differences in how tools and vendors interpret the 1300+ page specification, and there is no reliable source documenting these variations. The Universal Verification Methodology Manual (UVM) is 450+ pages, and many other standards are similar in length. Varying interpretations and implementations are inevitable.

Despite this, users expect the vendors to work out any interoperability issues so they don’t have to. They expect that commercial design IP and tool-generated RTL code will be accepted by all synthesis tools and yield functionally equivalent designs. They expected that verification IP (VIP) and generated testbench code will run the same way in all simulators. If there are problems, users have every right to expect that EDA vendors will cooperate to ensure smooth integration. This is precisely the motivation for most partnerships, and most EDA and IP companies have official partnership programs.

At Agnisys, we have our Fusion Partner Program, in which we invite services and training vendors to join with us for the benefit of our mutual customers. We are also a member of the partner programs for several other companies. In most cases, these programs are reciprocal, with both companies providing tools, design IP, and/or VIP to each other. Partnership agreements often include directly competitive products; these are shared under strict terms that require they be used only to test multi-vendor flows and resolve issues before they cause problems for users.

Agnisys is in an interesting position because we have differentiated solutions and little product overlap with other companies. We have found most EDA and IP vendors eager to work with us to ensure that our mutual customers have a seamless experience. Our tools generate RTL design IP, UVM-compliant testbench and tests, Portable Stimulus Standard (PSS) models, C/C++ code, and documentation in many formats. Our goal is to be able to validate that all these output files work properly with the leading solutions for logic synthesis, simulation, PSS, formal verification, C/C++, and documentation.

Agnisys is also unique since our products span such a wide range of system-on-chip (SoC) development activities and the groups involved in SoC projects. For example, our generated C/C++ code may be used by the verification team in system validation, silicon bring-up teams, and embedded software teams developing firmware and drivers. We provide solutions for architects, designers, verification engineers, programmers, and technical writers developing end-user documentation. The range of our partners reflects the range of our users.

I’d like to give a shout-out to a few of the partners who have been incredibly helpful and supportive in our quest to meet our validation goal. Our earliest partner was Mentor Graphics, who first provided simulator licenses to us way back in 2008. We have enjoyed a great relationship ever since, and it continues now that the Mentor name has been retired in favor of Siemens EDA. Today, in addition to simulation, we use Siemens tools to validate our generated assertions in formal verification as well as our generated PSS models.

Cadence is also an important and supportive partner, providing tools to validate our generated PSS models and our generated SystemVerilog design and verification code in simulation. Despite their huge size, both Siemens and Cadence understand the importance of partnerships for the benefit of users with tools from multiple vendors. Both companies also recognize that much of EDA innovation occurs in smaller companies, so helping to enable Agnisys (and many others) is ultimately a benefit to the entire industry.

We partner with other vendors with whom we have common interests or shared users. We validate our generated SystemVerilog with Aldec simulation and validate our generated assertions with the formal tools from OneSpin. Both companies are great partners, willing to go the extra mile when interoperability issues arise. We use the FPGA synthesis flows from Intel (formerly Altera) and Xilinx to check our generated RTL designs. All these partnerships help the EDA ecosystem and make the lives of design and verification engineers much easier.

It is unfortunate that not all vendors recognize the value of partnering for the benefit of users and the growth of the EDA and IP business. If there is a company that you’d like to see working with us, please let me know and, more importantly, please tell them that they should partner with Agnisys. Ultimately, we’re all in this together, trying to produce the incredibly complex electronics products that drive every aspect of our modern world.

Anupam Bakshi

Tags: EDA, SystemVerilog, testbench, UVM

This entry was posted on Tuesday, January 26th, 2021 at 9:32 pm. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.