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 Agnisys Automation Review

Archive for February, 2020

From specifying registers in SystemRDL to implementing the test intent using PSS

Friday, February 21st, 2020

The complex SoCs of today typically contain thousands of registers, which are used to control the operations of the SoC/IP. The register specification, which is at the epicenter of a SoC/IP design is accessed by different teams such as hardware, software, verification and embedded design teams, all of which need to access the same source. A mismatch and misinterpretation of the specification simply results in un-necessary delays to the development cycle.

While there are several methods to define the register specification, such as Excel, Word, IP-XACT etc., SystemRDL is gaining popularity, as it is an easy-to-use textual language used for the design and delivery of SoCs/IPs. Released by Accellera, SystemRDL supports the complete project cycle of registers from the specification, model generation, and design verification to maintenance and documentation. It mitigates the problems encountered in describing and managing registers. SystemRDL enables a system architect or a hardware designer to create a functional specification of the hardware-software interface (HSI) for an SoC/IP, which can include addressable registers, interrupts, counters etc. This specification is then used by other members of the team including software, hardware and design verification to create representations of data in the languages they use in their aspect of the SoC development process.

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Adopting New Methods For Faster Development Of RISC-V based SoCs

Monday, February 3rd, 2020

The growth of new technologies such as artificial intelligence, machine learning, Internet of Things (IoT), virtual/augmented reality and of course, the various technologies for the automotive industry has led to a new surge in the development of semiconductor chips. The growth had been stunted in part due to the considerable cost involved in using the processor core, which forms the heart of most SoCs. The enormous cost, risk, development time and necessary volumes of developing a processor, has kept this lucrative industry in the hands of just a few companies. That is, until now.

With the development of the open source RISC-V ISA from UC Berkeley labs, based on the new computing needs in various power and performance dimensions, the semiconductor industry is once again at the cusp of embracing an incredible surge in innovation. Over the last few years, the interest in RISC-V has been gaining steam with commercial implementations and adoption growing rapidly.
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