The TSN_CTRL implements a configurable subsystem meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards. It integrates hardware stacks for timing synchronization (IEEE 802.1AS) and traffic shaping (IEEE 802.1Qav and 802.1Qbv), and a low-latency Ethernet MAC.
The subsystem is designed to enable high-precision timing synchronization and flexible yet accurate TSN traffic scheduling. Requiring no software assistance for its operation, it features minimal and deterministic ingress and egress latencies, and simplifies the development of time-aware applications.
While operating autonomously, the TSN_CTRL provides the system with timing information (time-stamps, alarms, etc.) that is typically required for the operation of a TSN network bridge or node. Furthermore, it allows the system to define and tune in real time the traffic shaping parameters according to an application’s requirements.
The TSN_CTRL uses standard AMBA® or Avalon® interfaces to ease integration. Its configuration and status registers are accessible via a 32-bit-wide AXI4-Lite or Avalon-MM bus, and packet data are input and output via AXI-Streaming or Avalon ST interfaces with 8-bit data buses.
The TSN_CTRL subsystem is designed with industry best practices, and is available in synthesizable RTL (Verilog 2001) source code or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation.