Silicon Creations 
Short Desc. : Core Voltage De-Skew PLL TSMC 16nm FF+C
Overview :

The Silicon Creations Programmable De-Skew PLL is a high bandwidth, low jitter design optimized to minimize phase skew at its inputs. Wide input and output ranges along with best-in-class jitter performance allow the PLL to be used for almost any de-skew application. With excellent supply noise immunity, the PLL is ideal for use in noisy mixed signal SoC environments. By combining ultra-low jitter output clocks into a low power, low area, widely programmable design, Silicon Creations can reduce risk and time-to-market by enabling a single macro to be used for any clock de-skewing application.

Features : - Input frequency range: 4.17MHz to 1066MHz
- Feedback frequency range: 4.17MHz to 1066MHz
- Output frequency range: 4.17MHz to 4266MHz
- Static phase error (max, 3σ): ±3% of Input Unit Interval (< 2ps RMS @ 1042MHz FPFD, 4266MHz FVCO
- 4:1 VCO frequency range
- Core voltage only power supply simplifies integration
- Separate core voltage analog supply for optional noise isolation
- Lock Detect Signal indicates when frequency lock has been achieved
- Low area (0.02mm2 )
Categories :
Maturity : Mass Production
Portability :
Type :
 Hard IP 
Foundry :
Nodes :
Process :

Deliverables : - FE Design Kit: LEF Footprint, Behavioral Verilog Model, Liberty Timing Model, Application note (usage guidelines)
- BE Design Kit: GDSII Layout, Calibre LVS Netlist, DRC, LVS, ERC logfiles, Release note
DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IoTPLL

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