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 CAST, Inc. 
Part Number : SFLASH-AHB
Short Desc. : Single, Dual, Quad, and Octal SPI Flash Controller with XIP & DMA, for AHB
Overview :

The SFLASH-AHB core is a versatile SPI flash memory controller. It allows a system to easily access an SPI flash device or directly boot from it.

The core allows the system to interface with one or more serial flash devices in one of the following modes: a) in Slave mode by accessing its registers via an AHB slave interface, b) in DMA mode where the system programs the internal DMA engine, and then the core accordingly drives its AHB master interface, c) in eXecute In-Place (XIP) mode where the core allows the system to directly access the SPI memory address space via an AHB slave interface, d) in Boot-Image copy mode where after reset the core will autonomously copy an amount of data (boot-image) from the SPI memory to the AHB address space (e.g. on a shadow RAM) using its AHB master interface.

The core can work with single, dual, quad, twin-quad, and octal SPI flash devices. To enable use with flash devices from different vendors, the core offers two ways of configuring the device-specific parameters: a) via registers, where the system is responsible to identify the connected flash device and program the appropriate values to the core's registers and b) by using the auto-configuration feature, where the core will autonomously identify the connected flash device and program itself accordingly. The auto-configuration functionality uses a user-provided memory that stores a list of automatically identifiable devices along with their features.

The SFLASH-AHB can be easily configured to match different application requirements. Data and address width of the AHB interfaces, instantiation of the DMA engine and the auto-configuration logic, maximum number of Flash devices that the core supports, and reset values for all configuration registers, are some of the design parameters that can be controlled by means of simple Verilog defines.

This core has been designed with industry best practices. It is LINT-clean and scan ready, it has been verified through rigorous verification, and it is silicon-proven.

This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements. 


Features : - SPI NOR- and NAND-Flash controller supporting XIP and STR or DTR over single, dual, quad, twin-quad, and octal SPI links.

- Flexible Flash Access Modes
- XIP - Allows AHB bus masters to read directly from the flash with zero software overhead.
- DMA – Optional DMA engine can be programmed to transfer data from/to system to/from the Flash device
- Boot-Image Copy - After reset the core uses its
- DMA engine to autonomously copy an amount of data from Flash to the AHB address space
- Slave Mode – System accesses core registers to transfer data to/from the Flash
- Easy Integration & Operation
- Flash Device-independent. The flash device parameters can be set in the following ways:
- Automatically after reset. A list of automatically identifiable devices is provided to the core in an external memory
- At run time via configuration registers programming
- At synthesis time. Verilog defines for reset values of all configuration registers
- Zero software overhead with XIP and optional auto-configuration
- 32-bit and 64-bit AHB bus interfaces. Data-bus widths are configurable at synthesis time
- Configurable SPI interface:
- Single, Dual, Twin-Quad and Octal SPI

- Single Transfer Rate (STR) or Dual Transfer Rate (DTR)
- 4, 8, 16, or 32 bit word transmissions per data line
- Full and Half Duplex operation
- Configurable number of slaves (Chip-Select lines)
- Programmable serial clock polarity and phase
Categories :
Tags : SPI/QSPI Flash Controller with XIP & DMA, for AHB
Portability :
Type : Soft
Deliverables : - Verilog RTL source coder or targeted FPGA netlist
- User Documentation
- Testbench and sample synthesis and simulation scripts
DAC2018



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