Part Number : dwc_adc14b2msar_tsmc40ulp
Short Desc. : 14-bit, 2.5MSPS, 3.3V SAR ADC with 20:1 Differential Input Mux in TSMC40ULP
Overview :

With more than 15 years of experience in developing analog IP solutions, Synopsys offers a comprehensive portfolio of more than 100 silicon-proven DesignWare® Data Converter IP products consisting of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), auxiliary converters, video DACs (VDACs) and analog front-ends (AFEs). Synopsys' strong application expertise in areas such as mobile communications and wireless connectivity (i.e., LTE/LTE-A, WiFi.11n, WiFi.ac), wireline communications (i.e., G.hn, MoCA), IF demodulation, multimedia, imaging and video, and sensors and embedded applications, enables us to deliver high-quality data converter IP that helps system-on-chip (SoC) designers meet the specific design requirements for their target applications. The DesignWare Data Converter IP products offer very high performance, high speed, ultra low power dissipation, small area use, and support for a wide range of foundry process technologies ranging from 180-nm to 28-nm. Synopsys' high-quality DesignWare Data Converter IP solutions have been implemented in more than 200 SoCs, giving designers confidence that they can successfully integrate high-performance analog IP into their designs with less risk and improved time-to-market.

Features : - #1 provider of data conversion IP for nine years in a row (Gartner 2012)
- Over 15 years of delivering proven data conversion solutions
- Supporting all communication protocols, leveraging extensive application expertise
- Complete portfolio of silicon proven IP includes: High-performance, high-speed 10- and 12-bit at 320 MSPS ADC and 12- and 14-bit at 600 MSPS DAC
- Complete portfolio of silicon proven IP includes: General-purpose, high-resolution ADCs, auxiliary DACs and VDACs
- Compact design and ultra-low power dissipation
- High-quality IP and excellent support
- Robust, fully validated solutions
- Highly flexible solutions
Categories :
Maturity : Available on Request
Portability :
Type :
 Hard IP 
Foundry :
Nodes :
Process :

Deliverables : - Databook
- Behavioral Verilog model
- Abstract LEF and timing LIB files
- CDL Netlist for LVS; GDSII layout database
- Assembly guidelines and full integration support
ClioSoft at DAC

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