The AES-XTS encryption IP core implements encryption/decryption for sector-based storage data. It uses the AES block cypher, in compliance with the NIST Advanced Encryption Standard, as a subroutine. The core processes 128 bits per cycle, and is programmable for 128- and 256-bit key lengths.
Two architectural versions are available to suit system requirements. The High Throughout version (AES-X) is more compact can process 128 bits/cycle. The Higher Throughput version (AES-X2) can process 256 bits/cycle.
The AES-XTS core is a fully synchronous design and has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.