The AES-XTS encryption IP core implements encryption/decryption for sector-based storage data. It uses the AES block cypher, in compliance with the NIST Advanced Encryption Standard, as a subroutine. The core processes 128 bits per cycle, and is programmable for 128- and 256-bit key lengths.
Two architectural versions are available to suit system size and throughput requirements. The XTS-X is more compact and can process 128 bits/cycle independent of the key size. The XTS-X2 can process 256 bits/cycle independent of the key size. Both versions have a 128-bit data path.
The AES-XTS cores are fully synchronous design and have been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs.
This core can be mapped to any any Intel, Lattice, MicroSemi, or Xilinx programmable device, or to any ASIC technology, provided sufficient silicon resources are available. Please contact CAST Sales to get accurate characterization data for your specific implementation requirements.