Division of Labor - March 17, 2003

Well, maybe not divine, but certainly unavoidable, expensive, often inefficient and incomplete, yet (almost) always critical to the success of a project and to the level of subsequent customer satisfaction - particularly in multi-million gate designs produced with next-generation process technologies.

But if you've been out and about at technical conferences lately, you may have heard rumors of strategic personnel cutbacks that keep the designers, but eliminate dedicated verification engineers for the sake of the bottom line.

How can this be? How can the industry continue to pay lip service to well-verified designs, when personnel crucial to verification are being laid off? Are the current verification tools capable of picking up the slack? Can the current crop of design engineers handle these tools with the same skill and familiarity as a modern-day verification engineer? Or instead - are all of the rumors simply unfounded?

A variety of verification tool vendors were asked to respond to these questions, and their answers are listed below. Their responses are not identical and it's interesting to discern the subtle distinctions between their opinions. It was tempting to leave the names of the companies off of their responses, to disconnect a company's technology initiatives from its philosophy regarding today's design & verify personnel conundrum. But can you ever separate a company's philosophy from its fundamental technology? Not really, so the names of the companies were left in place.

Meanwhile, after you've had a chance to read the various statements, you'll also have a chance to hear from Janick Bergeron, industry veteran and Moderator of the Verification Guild. He says his opinions on the design-versus-verification engineer issue are “well known.” Nonetheless, it's great to have him weighing in on the discussion and his input is appreciated.

So, consider this to be a panel discussion of sorts. There are 12 panelists and an expert moderator, ready to attack the topic at hand. Read on and learn what you will.

(Editor's Note: The responses here are verbatim, as received. Thanks to all who took the time to respond and to contribute to the dialog. I am particularly grateful to those who refrained, as much as possible, from inserting marketing language into their comments.)

Once again, here's the question:

“Voices in the industry seem to be indicating that many companies cannot afford to - or choose not to - have a separate individual on the design team who handles verification. Therefore, are the verification tools currently available easily understood and used by design engineers who are NOT verification engineers? In other words, are verification engineers no longer needed?”

And here are the answers:

Emil Girczyc, CEO and President at 0-In Design Automation, Inc. - “The trend to having the same person design and verify has been a standard practice in software development for many years. This makes testing more effective because the tester knows both the specification and implementation enabling both black and white box testing. But more importantly, programmers learn to write code that is testable. Placing assertions in C code is common coding practice, as is documenting interfaces, documenting the internal code structure, and most importantly, writing testable code.”

“In the case of hardware design, having designers participate in testing also will lead designers to better instrument their code, document their interfaces, document their RTL structure, and design testable circuits to simplify verification. There is no clearer way to get a designer to appreciate the benefits of design for verification than forcing them to do some verification. The tools that designers need to achieve design for verification are a coding guideline, a rich library of assertion IP, and robust tools for assertion-based verification. Once established, these tools and practices are easy enough for most designers to use to the level required for design for verification.”

“However, when the only code checker is the designer that wrote the code, there are holes for many bugs to slip though. In software development, every programmer's code is also tested by other developers, specialists, and customers (alpha and beta testing), and there is always someone who builds a test infrastructure that each programmer leverages. Similarly in hardware development, others need to test each designer's RTL code to insure that the designer hasn't misread the spec, or missed implementing or testing a part of it. Further, since the hardware equivalent of a “beta” or a patch release is very expensive - a silicon re-spin potentially greater than $1 million, several months' delay, and possibly a field recall - hardware requires more rigorous testing of the RTL implementation than does C code.”

“This will likely be done by verification specialists (or designers acting as verification engineers). There will also always be a role for someone on the team who (full-time or part-time) sets up the infrastructure for regression testing, metrics, etc. that will be used by all verification engineers. This is not just a function of running the tools, but having the extra insight and time to plan a methodology and set up the infrastructure to make verification robust, effective, and efficient.”

Dino Caporossi, Vice President of Corporate Marketing at Verplex Systems Inc. - “When using Accellera's Open Verification Library (OVL), there are few people better to insert the assertions than the designer since he or she is the one who understands how the design should be verified from an implementation point of view. When a designer creates a First In First Out (FIFO) block, for instance, the designer automatically knows that it should be checked for overflow (writing when already full) and underflow (reading when empty). The verification engineer typically stays at a higher level and does not check for such things. Then, errors that could have been caught earlier by the designer are caught later by the system-level or verification engineer. But at that point, the design has matured to the point where fixes are more difficult and expensive to make.”

Francine Ferguson, Vice President of Corporate and Strategic Marketing at Verisity - “Are verification engineers no longer needed? Absolutely not! Verification has become the most critical business problem electronic companies are facing and hence, verification engineers are becoming more vital to engineering teams than ever before. When tackled correctly - with a mix of experienced engineers, the right methodology, and cutting-edge technology - verification can provide the biggest productivity gains in the entire design schedule. Of course for many companies, separate verification teams, or engineers with the title Verification Engineer, may not exist. But when it comes to doing system-level verification, they actually do have specialists responsible for the verification that are, in fact, equivalent to a verification engineer.”

Udo Muerle, CEO of TransEDA - “Verification engineers are needed more desperately than ever, so I think the question of whether the tools are easy to use is not the key issue. A verification engineer needs to address and resolve very different issues compared to a design engineer. But both require the best tools available for them to do their job. In chip design today, the most pressing problem is to verify that all functionality integrated into a design will work correctly. In comparison, it is relatively easy to integrate the required functionality, as it is now commonly achieved through IP use. So the question should be: 'How much effort should be spent on verification?' It is well documented that 70% or more of total design time is spent on verifying the design. This underlines the necessity for verification. Companies cannot afford to not have engineers whose responsibility is focused on making sure a design works as it should.”

Rajiv Kumar, COO, Vice President and Co-Founder of Real Intent - “It is safe to say that the verification engineers are going to be needed for the foreseeable future. But it also is equally safe to say that new verification tools are now empowering the designers to perform verification tasks that have traditionally been done by the verification engineers. More specifically - assertion-based verification (ABV) tools are leading that transition. For example, our formal ABV tool Verix is being used regularly by designers to formally verify behaviors of their blocks with designer-provided assertions. This is taking place well before they hand-off the RTL to the verification teams. Similarly, the designers are also using Verix to verify multi-clock designs to ensure that signals are safely crossing asynchronous clock domains.”

Dave Ruggiero, Vice President of Marketing at Pittsburgh Simulation - “Our mission is to dramatically reduce the verification time of complex semiconductor designs and shorten time to market. Getting rid of verification engineers is not a trend we see at the major design houses. Designs that contain millions of cells require the skills of verification engineers. They are an integral part of the design process for large, complex designs. But for smaller, less complex devices, designers alone may be able to address verification.”

Scott Sandler, President at Novas Systems, Inc. - “Our debug systems tools work with all the popular simulators and other verification tools to help users understand the causes of design behavior. We have many design engineers and verification engineers in our customer base. Over the past several years, we've seen a pretty constant mix with respect to how companies organize their design and verification resources. Some create separate groups, some assign engineers specifically to verification for the duration of a project, and some divide the responsibility among the same people over the course of a project. (“You verify mine and I'll verify yours.”) I'd say, we find about half of our customers dedicate separate people to verification, and we've seen no evidence to support the notion that the mix is changing.”

Robert Hum, Vice President of Design Verification & Test Division at Mentor Graphics Corp. - “Whether or not a verification engineer is part of a team depends on a number of factors, including the type of design, the size of the company, and the existing verification methodology. We see teams with and without verification engineers. The most popular verification tool today is still an HDL simulator, like ModelSim, and most testbenches are still written in VHDL and Verilog. Both designers and verification engineers already have extensive experience with simulators. We think that strategies that expand existing platforms, like adding mixed-language simulation and code coverage to ModelSim, help users increase verification productivity faster by leveraging their existing knowledge. Simulator companies will continue to add functionality to their tools, because their customers ask them to.”

Dian Yang, President and CEO at InnoLogic Systems, Inc. - “Design and verification engineers have separate and important functions. The design engineer is responsible for interpreting the specification and implementing the design, while the verification engineer is responsible for validating that the design will operate according to its intent, especially within the system context. As migration to 90-nanometer process technology is increasing the complexity of SoC designs, the role of verification engineers continues to be critical. Formal verification tools such as our ESP-CV help the verification engineer to validate the design intent against the design implementation of critical full custom elements such as memories, datapath, and IOs that are increasingly consuming today's SoC designs.”

Lauro Rizzatti, Vice President of Marketing at EVE (Emulation and Verification Engineering) - “By consensus in the electronic industry, design verification burns 70% or more of the development cycle. The culprit is two-prone - on the one hand, complex and difficult creation of effective test environments, on the other hand, poor to extremely poor processing speed of such test environments. The industry responded in two ways - by inventing new hardware verification languages (HVLs) to help the creation of efficient test suites, and by resorting to hardware-assisted verification solutions to accelerate the execution speed of these test suites. Unfortunately, the above solutions either require skills that designers are reluctant to develop or resources that are scarcely available to designers.”

“To fully exploit the considerable verification efficacy of an HVL, a designer must learn a new verification language that he/she would rather relinquish to a verification engineer. To effectively use a hardware-assisted solution, the user must spend precious time to setup the hardware-based verification environment, and considerable financial resources to acquire such a system - propositions that a designer would happily hand over to a verification department. The real answer to the problem can only come from a verification solution that combines the power of the HVL methodology, but is made easy to learn, with the performance of emulation, packed in a small footprint and sold for a fraction of the current emulation prices.”

“Empowered by such a solution, a hardware design department will mirror the development methodology of most software development centers. As each software developer completely verifies his/her piece of code, leaving to a QA team the validation task of the entire software system, so a hardware designer will thoroughly test his/her hardware module and a system verification team will then perform system integration and carry out the time-consuming regression testing.”

“At EVE, we have addressed one of the two causes of the problem by devising ZeBu, a desk-top, high-end emulator. Inserted into every designer's PC/workstation, one or more ZeBu cards can speed up the most complete test environment by several orders of magnitude. We are looking forward to a new breed of HVL solutions that will work in concert with ZeBu and together propose the final answer to the demanding task.”

Steve Wang, Vice President of Marketing at Axis Systems - “The need for verification engineers is not going away, but their place in the design methodology is expanding and moving higher in the design flow. As the industry moves towards the next level of abstraction (Electronic System Level or ESL), these engineers need tools that give them visibility into both hardware and software components of the design much earlier to verify the design is viable along each step of the process. So the tools are not replacing verification engineers, but facilitating their jobs as design and verification become parts of a single methodology.”

Charles Miller, Senior Vice President for Marketing and Business Development at Aptix Corp. - “Our recent customer survey indicates a merging of design and verification groups. (63% say that the Design Group and the Verification Group are one and the same. 31% say that the Design Group and the Verification Group work very closely with each other. 6% fall into the category we call “Other.”) We believe this is driven by increasing design complexity and the need to validate designs under real-world operating conditions. This often requires design knowledge that only resides with the developers.”

The Moderator Weighs In ...

Janick Bergeron, CTO at Qualis, Inc. - “There are many components and facets to the statement. Let me try to address them individually”

a) “Many companies cannot afford to - or choose not to - have a separate individual on the design team who handles verification.”

They choose not to, consciously or otherwise. The work that must be accomplished to design and verify a successful ASIC is constant, regardless of how you choose to distribute it between your engineers. It's a fixed pie. You can let everyone do some design and some verification, or you can let some do all of the design and some do most of the verification. Some distributions will be more efficient than others. But it is a distribution issue, not a technical or financial one.

The other obstacle is cultural. Design is still perceived as more sexy or “fun.” Verification is perceived as boring. Personally, being limited to a coding style imposed by a synthesis technology that is 15 years old is what I find boring and passé. Verification is where the action is - in new methods, tools, and standards. I've been doing verification for 12 years - and I'm always learning something new.

b) “Are the verification tools currently available easily understood and used by design engineers who are NOT verification engineers?”

No more or less than a physical synthesis tool is easily understood and used by a verification engineer. If you are doing a small, low-speed design that does not push the limits of the EDA technology, you can understand and use all of the design and verification tools required to accomplish your job. But for those large, high-speed designs that require an intimate knowledge of the deep-submicron issues and physical synthesis in order to reach timing closure, the complexity of the verification requires expertise in object- or aspect-oriented programming, configuration management and high-level modeling. These skill sets have no overlap and require different background expertise - the former in device physics, the latter in software engineering.

At the height of the Greek and Roman empires and in the Middle Ages, it was possible for an individual to know and understand all of the human scientific knowledge of the time. But as the quantity and complexity of technology started to increase, individuals had to become specialists. The more complex the technological advances, the more numerous the specialists. ASIC design cannot escape this simple truth of human nature: as design has been split into architects, hardware designer, back-end engineers, manufacturing and test engineers, further splits - such as design and verification - are bound to occur and must be embraced.

One strategy that can help bridge the concept gap between designers and state-of-the-art verification tools is the use of verification IP (either assertion or simulation). Using verification IP does not require the same level of expertise and knowledge as writing them in the first place. They can be an effective mechanism for shortening time-to-first-test and starting a design team on the verification methodology learning curve. Note that the challenges of making a testbench component reusable are different (but as complex) as making a design component reusable - highlighting again the differences between the design and verification methodologies.

c) “Are verification engineers no longer needed?”

Current economic conditions may simply dictate that additional engineers, hired specifically as verification engineers, are no longer affordable - so design teams will have to make do with what they have (and I fundamentally believe that it should force some of the current staff into verification engineering). Assertion-Based Verification also carries the myth that design engineers, by inserting those magic incantations in their RTL code, will suddenly accomplish the bulk of the verification. ABV definitely improves the quality of a design and eases debugging - but they still require a testbench (until formal technology can replace simulators) to exercise the design so the assertions can be triggered. And assertions can only deal with very localized issues. No assertions can verify the proper reassembly of a set of concurrent out-of-order packet fragments, or the execution of a set of instructions, or the enumeration of a USB network. That still requires a self-checking, high-level (preferably constrainable randomly generated) simulated verification environment.

Some verification will always be performed by the design engineer, the “kick the tires” verification that demonstrates that the module or unit has some hopes of interacting properly in its environment. But the bulk of the verification - creating corner cases, pushing a lot of data and configurations through the system, creating (with the help of the designers) a verification plan and functional coverage model - needs the undivided attention of verification engineers. Having the same engineers doing both design and verification creates a big “hump” in the number of testcases and testbenches that must be written and debugged once the RTL is done and every one “switches over” to verification - which often requires contractors to meet the original schedule. In contrast, a dedicated verification force can start addressing verification much sooner (usually with the help of functional models) with a more predictable and smoother schedule. Once the RTL is “done,” designers are kept busy by the large number of bugs such a team usually turns up - hopefully many quickly identified and diagnosed using assertions.

(Editor's Note - Thanks, Janick, and to all of you for contributing to this conversation.)

Industry News - Tools & IP

Actis Design, LLC announced AccurateC Rule Generator, which is SystemC-based software that allows designers to create user-defined rules in C/C++, based on project specifications. AccurateC Rule Generator is a companion product to the company's AccurateC Rule Checker, a SystemC-based language rule checker. The company says the tools help engineers to produce design-ready SystemC code and promote design reuse. Additionally, the company announced that is has named PrimeGate Ltd. of Tokyo as its distributor in Japan.

Agilent Technologies Inc. announced that STMicroelectronics selected Agilent's RF design environment (RFDE) for RF/mixed-signal IC design. The company said that STMicroelectronics has begun to upgrade their R&D operations to the Agilent and Cadence Design Systems RFDE-based design flow. RFDE is an RF EDA software platform that integrates RF simulation technologies from Agilent's Advanced Design System into Cadence's analog and mixed signal design flow. RFDE is the first product to result from the Agilent/Cadence alliance.

Altium Ltd. announced the release of CAMtastic DXP and a free ODB++ capable CAM viewer based on this new version. The company says that “CAMtastic DXP is the latest version of Altium's complete CAM verification and editing system that bridges the gap between PCB design and manufacturing and facilitates communication between board designers, fabrication engineers, and their clients.” CAMtastic DXP's new features include bi-directional ODB++ support, advanced panelization, additional DRCs for strengthened data verification, and numerically controlled drill and rout features. The company - headquartered in Australia, with offices in Asia, Europe, and North America - says that its Windows-based EDA products are positioned in a price/performance range to meet the needs of the population of board designers who do not need high-end tools from Cadence and Mentor.

ARM announced the availability of version 2.0 of its RealView compilation tools, a component of the RealView development solution supporting the new ARM C/C++ EABI (Embedded Applications Binary Interface) standard. New to version 2.0 are ISO C++ support including namespaces, full template support, and real-time type information (RTTI). The compilation tools also provide support for all of the ARM processor families. The ARM C/C++ EABI is a cross-platform standard developed in collaboration with operating system (OS) and tools vendors, which specifies how executables and shared objects work together for OS or other execution environments. The company announced that Symbian Ltd. is adopting the ARM CC++ EABI system for the Symbian OS.

Barcelona Design Inc. announced the release of version 1.2 of the Prado analog synthesis platform, with an expanded ability to produce a product-specific analog IP block for SoCs. Version 1.2 of the synthesis platform has several new features, including trade-off analysis capabilities, which allow the designer to evaluate performance trade-offs between different automatically synthesized circuits to evaluate system-level requirements.

Cadence Design Systems, Inc. and Semiconductor Manufacturing International Corp. (SMIC) jointly announced that SMIC has qualified one of its first-generation reference flows. The flow incorporates the Cadence Encounter digital IC design platform. The SMIC reference flow was developed using SMIC's 0.18-micron process technology. The companies say that the SMIC-Cadence Reference Flow 1.0 is a complete RTL-to-GDSII flow and includes logic synthesis, simulation, silicon virtual prototyping, and physical implementation. SMIC is the first pure-play advanced IC foundry in China to achieve volume production for 8-inch wafers at 0.25 micron and finer line technologies, and was established in April 2000. SMIC is a Cayman Islands company based in Shanghai.

Also from Cadence - The company announced a new capability for designing stacked-die packages integrated into the Cadence Advanced Package Designer Suite. The capability supports all phases of design and includes the ability to bond as many dies as desired, to use different spacing rules for each die and quadrant, and to create multiple bonding patterns so that one substrate can handle multiple-die combinations. Advanced Package Designer also provides a capability for combining flip-chip and wirebond die in the same design. The company says that stacked-die packages are particularly common in cell phones, digital cameras, and hand-held devices, which require faster turnaround, higher levels of integration and the lower costs associated with system-in-package (SiP) products.

And from Cadence, as well - The company announced a new methodology for designing and implementing multigigabit serial interfaces in high-speed PCB systems. Complex multi-board backplane applications can have hundreds or thousands of differential signal pairs, and long cycle times, as engineers perform numerous layout-simulate-fix iterations. Keith Felton, Product Marketing Group Director, PCB Systems Division, says, “This new methodology is a virtual environment that gives the engineer a topological view and allows simulation data to be turned into constraint-driven design.” The environment permits engineers to design a comprehensive set of rules within Constraint Manager, and then use those rules to drive layout and routing. The new differential signal capability is part of the 15.0 release of the Cadence PCB Expert series design environment.

InnoLogic Systems, Inc. and Novas Software Inc. announced that InnoLogic has joined Novas' Harmony partner program. The two companies say they have a long-standing relationship in that users of InnoLogic's ESP-CV, a product that verifies the functional equivalence between behavioral or RTL models and the SPICE-level netlist of full custom designs, can use Novas' Debussy Debug System to investigate model mis-match. They also say that InnoLogic's membership in Novas' Harmony program will improve the interoperability and support that the companies provide for mutual customers.

InTime Software, Inc. announced that Time Builder, a time-driven hierarchical floorplanner, has been named one of the Top 100 products of 2002 by EDN Magazine. The magazine awards products that generate significant interest because of usefulness and innovation. Time Builder allows any combination of RTL and gates to be input to the system. The tool contains a built-in static timing analyzer and links to synthesis to allow designers to identify timing problems and optimize logic through either gate-to-gate re-synthesis or RTL-to-gate re-synthesis.

Mentor Graphics Corp. announced that Toshiba Corp. has selected Mentor Graphics ADVance MS (ADMS) tool, a mixed-signal, mixed-level IC simulator, for use in Toshiba's IC design flow. Toshiba says it will use ADMS for its mixed digital-analog CMOS and BiCMOS SoC designs. ADMS uses a single kernel engine that combines the ModelSim VHDL/Verilog simulator, AMS HDL language in VHDL-AMS and Verilog-AMS, and Eldo, a transistor-level simulator.

MLDesign Technologies announced the availability of version 2.4 of MLDesigner, an integrated “mission-level” design platform, that the company says offers better performance, distributed external simulations, expanded run control capabilities, and support for the GNU C compiler 3.X. Improved run control capabilities are intended to provide new options for stepping through simulations to analyze simulation execution while monitoring critical events, and to track the execution of external simulations. MLDesigner 2.4 includes a new family of probes, which can be combined with breakpoints, graphic animation, and run controls to extend debugging capabilities. Probe outputs can be displayed dynamically during simulation or written to files for later analysis.

Tera Systems announced that its TeraForm RTL Design Consultant (RDC) and Virtual Prototype (VP) technologies have been selected for inclusion in the NEC Electronics' Instant Silicon Solution Platform (ISSP) OpenCAD design flow. NEC says it chose the Tera Systems TeraForm product to “simplify the customer design flow for ISSP designs and increase performance predictability.” The NEC Electronics ISSP is a new class of ASIC device based on a high-integration, “easy-to-design” ASIC architecture, which targets mid-volume designs.

Industry News - Devices & Fabs

Agere Systems announced 21 transistors intended for the wireless basestation power amplifier market. The company says the new products are “the world's coolest temperature wireless radio frequency power transistors.” Agere believes the transistors will help to shrink the size and shift the location of a typical basestations, from the size of a backyard toolshed and installed on the ground to the size of a suitcase and installed above the ground on wireless antenna towers. The company also believes the new transistors will reduce the number of cooling fans in base stations, compared with hotter transistor products, and reduce noise pollution in the vicinity of basestations.

Also from Agere - The company announced an integrated multimode wireless LAN chip set that permits “seamless” connectivity to 802.11a, b, and soon-to-be deployed 802.11g networks. The multimode chip set includes a single-chip, dual-band RF transceiver. The RF chip can operate in both 5 GHz and 2.4 GHz frequency bands. The radio is coupled with a multimode MAC, a multimode baseband processor, and a dual-band power amplifier to form an interoperable, single platform for both 802.11a/b and 802.11g wireless LAN applications. The product includes evaluation boards, reference designs, firmware and software drivers, certification utilities, manufacturing test software, and customer support, along with data transmission speeds of up to 54 Mbps. The company expects to deliver silicon samples in the second quarter of 2003.

AMD announced its low-voltage mobile AMD Athlon XP-M processors will be part of the new Fujitsu LifeBook S2000 notebook, which weighs less than four pounds and is 1.36” in height. This will be the first AMD processor-based thin-and-light notebook available in the U.S.

Infineon Technologies AG announced several product and business developments in its Wireline Communications Business Unit, which add to the Infineon portfolio of optical communications products - optical transceiver (TRX) modules that comply with the newly approved XFP standard; a family of “intelligent” small-form-factor pluggable (iSFP) TRX modules with data rates of up to 2.5 Gbps; a second generation of Infineon's parallel optical link devices, the PAROLI 2 family, with data rates of up to 3.125 Gbps; a joint PAROLI device marketing and product development agreement with Molex Inc., with all PAROLI products fully second-sourced by Molex; and the shipping of the TenGiPHY product, a 10-Gigabit Ethernet (10GE) XAUI-to-serial transceiver.

Intel Corp. introduced its fastest Intel Xeon processors, with performance above 3 GHz. The new processor at 3.06 GHz has a 512 KB level-two cache and a 533 MHz system bus, and is drop-in compatible with existing systems designed with the Intel E7501 or Intel E7505 chipsets. The 3 GHz Xeon includes a 512 KB level-two cache and a 400 MHz system bus, and is drop-in compatible with systems designed with the Intel E7500 or Intel 860 chipsets. Systems based on Intel Xeon processors are used as servers for web hosting, data caching, search engines, security and streaming media, and as workstations for various engineering and business applications.

Also from Intel - Intel Corp. introduced Intel Centrino mobile technology, which integrates wireless capability into a new generation of mobile PCs that the company says “will bring business users and consumers greater freedom to connect in new places and in new ways.” The Centrino technology includes a new mobile processor, related chipsets and 802.11 wireless network functions that have been optimized, tested, and validated to work together. In addition to wireless communications, the Centrino technology aims to extend battery life, allow for thinner and lighter notebook designs, and provide high-quality mobile performance. Intel CEO Craig Barrett said, “Unwiring the PC will change the way people use computers, allowing them to communicate, be productive or be entertained wherever and whenever they want. This breakthrough innovation, together with industry-wide investment and Wi-Fi hotspot deployments, brings new computing and communications capabilities to businesses and consumers, adding value to mobile PCs.”

Intel says: “Hotspots - locations where users can connect using 802.11 wireless technology - are on the rise. According to industry analyst firm IDC, there will be more than 118,000 hotspots worldwide by 2005. Using truly mobile notebook computers can change the way people live. A business traveler can check office e-mail or read the hometown newspaper on-line while waiting for a flight at the airport, and still have battery life left to watch a DVD movie on the plane ride home. A real estate agent can check the latest listings wirelessly while dining with prospective homebuyers. A financial planner can check the market and activate client orders while at a seminar without compromising on the performance necessary to run the most demanding office applications. Students can register for next semester's classes or seek a part-time job from the college library, all on a sleek, light-weight system that won't drag them down.”

MoSys, Inc. announced that the company's 1T-SRAM memory technology has now been silicon-proven on a 90-nanometer standard logic process. The 1T-SRAM memory uses a 0.61-micron square-bit cell design for an embedded memory density of 1.1 mm square per megabit. The company says this allows designers to integrate over 100-megabits of embedded memory on a standard logic device for SoC products, and that by incorporating MoSys' Transparent Error Correction (TEC) technology as standard for the 90-nanometer implementation of 1T-SRAM memory, the user avoids the cost of laser repair for large embedded memories while maintaining adequate yield, reliability, and low soft error rate. The measured soft error rate for 1T-SRAM test chips on the 90-nanometer process is under 4 Failure-In-Times (FITs) per megabit.

Motorola, Inc.'s Semiconductor Products Sector, announced a flexible IO expansion IC for microcontroller-based systems. The company says the MC33993 combines “flexible input and output features” and may eliminate the need for dozens of discrete and standard linear ICs in a design. Motorola also says that “in many systems, it may be the only device needed besides the MCU and a 3-pin regulator.” The MC33993 interfaces with a MCU through a four-pin serial peripheral interface and uses an analog multiplex feature to send up to 22 analog signals to one MCU A/D input. The 22 IO pins may be configured to detect the status of a switch contact, provide an analog value to a buffered output, drive an LED or the gate of an FET, or provide switched power to a low current sensor. The MC33993 also includes a low-current sleep mode.

National Semiconductor announced the LP387x family of low-noise CMOS low dropout (LDO) switching regulators for low voltage, high current applications. The six new products have output currents of 0.8 A, 1.5 A or 3.0 A, logic-controlled ON/OFF, either an error flag or a separate sense pin, and over-temperature and over-current protection. The typical dropout voltage for the regulators is a low 240 mV at 800 mA, 380 mV at 1.5 A, and 800 mV at 3.0 A load. The new product family includes the LP3871, LP3872, LP3873, LP3874, LP3875, and LP3876, and is characterized by an output voltage accuracy of +/- 1.5% at room temperature over load and line variations, and is guaranteed to be +/- 3.0% over all conditions. In applications where the load is remote from the regulator, the separate output sense pin allows sensing at the load, compensating for PCB trace resistance. The 10 nA quiescent current in shutdown mode permits Sleep or Standby operation. The LP387x family is currently available.

Oki Electric Industry Co., Ltd. and UMC announced today that a new ASIC product line will be introduced by Oki as a result of a business partnership between the two companies announced in September 2002. The new ASIC product line from Oki - the MG7xK family - uses UMC's 0.15-micron process technology.

QUALCOMM Inc. announced an agreement with Sun Microsystems, Inc. to develop and distribute Java 2 Platform, Micro Edition (J2ME Platform) virtual machine technologies. Support for J2ME will allow pre-existing Java applications to run on select QCT MSM chipsets, beginning with members of the 6xxx family of chipset solutions, and will have optimized performance through the use of the MSM's Launchpad suite of multimedia and other advanced technologies. Support for the Java runtime environment will also make QCT's chipsets compatible with other Java technology-compliant devices.

Teradyne, Inc. announced that the Haier IC Co. of Shanghai, a division of the Haier Group, selected Teradyne to assist in the design verification of a microcontroller for use in home appliances such as refrigerators, washers, air-conditioning units, and dish washers. The company says the selection was based on the results of a “competitive design-in” and on “Teradyne's strong applications and customer support infrastructure in China.”

Texas Instruments Inc. announced three new DSPs with performance characteristics clocked at 720 MHz. The company's previous DSP performance record was set at 600 MHz. The three DSPs are designed to increase multi-channel density, “multi-function flexibility,” and bandwidth. The devices are intended for digital video, imaging, and wireless/telecom infrastructure customers. The 720 MHz TMS320C6416, TMS320C6415 and TMS320C6414 DSPs are based on the TMS320C64x DSP core and produced on the company's 130-nanometer Cu-process technology. All three DSPs include 1 MB of on-chip high-speed memory.

Coming soon to a theater near you

Programmable World 2003 - Xilinx Inc. hosts this “collaborative industry forum” with sponsorship from IBM, Agilent, Cadence, Texas Instruments, Wind River Systems, The MathWorks, Mentor Graphics, Synplicity, Synopsys, Celoxica, Nallatech, and Altium. It's a free event where engineers can attend sessions on various technologies and methodologies. Forum organizers say that last year, 8,000+ engineers attended Programmable World 2002, while 10,000+ engineers are expected to participate this year. Scheduled for May 6th, the forum will be held simultaneously in multiple cities including Austin, Atlanta, Boston, Chicago, Columbia (Maryland), Dallas, Long Island, Longmont, Los Angeles, Ottawa, Phoenix, Raleigh, San Diego, San Jose, and Toronto. The forum will also be held later, in other locations throughout the world - Munich on May 15th, Shanghai on June 16th, Hsinchu on June 18th, Seoul on June 20th, and Tokyo on June 24th. ( www.xilinx.com/pw2003)

DAC 2003 - Of course, you already know you need to get to Anaheim in the first week of June to attend DAC 2003. Conference organizers have now announced that two stalwarts of the industry will give the keynotes. On June 5th, U.C. Berkeley's Dr. Alberto Sangiovanni-Vincentelli will address “The Tides of EDA” - his perspective on the cyclical behavior of the EDA industry, technology advances, and how the EDA and design communities need to collaborate to contribute toward the electronics industry's recovery. Maybe the industry will have recovered by June and he won't have to cover that last bit.

But first, on June 3rd, ARM's Sir Robin Saxby will present: “Less than 100 nanometers ... A Giant Leap for Mankind?” The question mark is probably the give-away here as Sir Saxby will be discussing what is undoubtedly a rhetorical question at best - whether or not the industry will be able to take advantage of all the additional transistors that will emerge from further pursuit of the holy grail of the semiconductor industry - Moore's Law. ( www.dac.com)

SEMICON West 2003 - It's not too soon to be penciling this mega-event into your PDA. Conference organizers say more than 60,000 people registered to attend SEMICON West 2002. They also say that “while there was a slight decline in overall registered attendance, executive management attendance increased 3% - thereby confirming that decision makers continue to place SEMICON West on their calendar as a must-attend exposition.” Whether you make decisions or not, you'll probably want to get to some or all of this show. The Wafer Processing portion runs from July 14th through 16th at Moscone Center in San Francisco, CA. The Final Manufacturing portion runs from July 16th to the 18th at the San Jose Convention Center. ( www.semicon.org)

Newsmakers

Pittsburgh Simulation Corp. announced the appointment of Roddy Beat as Director of European Operations, to set up European headquarters for the company. Plans include a system center with application engineering support in a European location to be announced soon. Previously, Beat was European sales manager for Cadence Design System's IMS group.

Tower Semiconductor announced that “longtime co-chief executives Dr. Yoav Nissan-Cohen and Dr. Rafi Levin have announced their intention to resign from service, after leading the company for 10 years and completing the main task of launching Fab 2 operations, the company's 0.18-micron and below manufacturing facility, which opened earlier this year.”

Idan Ofer, Chairman of the Board of Directors of Tower, said, “The board is extremely grateful to Yoav and Rafi for their dedication, vision and long years of service. Under their direction, Tower has grown from a single-fab operation to a multi-fab, multimillion-dollar operation with the infrastructure in place to advance to the next level.” Tower also announced that Idan Ofer has elected to step down as Tower's Chairman of the Board, although he will continue to serve on the Board. Carmel Vernia has been named Chairman of the Board and acting CEO of Tower. Vernia's appointment is subject to approval by Tower shareholders, and with such approval, the management changes announced will go into effect beginning June 1, 2003.

In the category of ...

Personal notes from PCB West 2003

Early last week, the NASDAQ celebrated the 3-year anniversary of its peak valuation in March 2000 by reaching a point fully 75% below that peak - an unbelievable collapse in value that few can really comprehend.

I celebrated that same anniversary by going to PCB West 2003 going on all week at the San Jose Convention Center. It was being co-located for the first time with HDI Expo 2003 - both shows managed by the newly established UP Media Group. The show was definitely smaller and quieter this year compared to 2001 when I last attended, but that's not surprising given the economic and international challenges that abound.

Lots has changed since I last saw Pete Waddell, Founder and President of UP Media, and his team back in early 2001 - national tragedies, economic unraveling, and now a possible war. But good things have happened as well. UP Media was formed when Pete purchased the Atlanta “books” from CMP Media - PC FAB, Printed Circuit Design, and Circuits Assembly - along with the related shows.

Ronda Faries, formerly Editor-in-Chief of PCD, is now Marketing Development Manager for UP Media reporting directly to Pete. She says that, although the past year has definitely tested the young company, the staff is more streamlined these days, they're up and running, and they're meeting the challenges of the new business day-by-day. That was good to hear and Pete echoed Ronda's up-beat evaluation.

The keynote speaker at the show was Nic Brathwaite, CTO at Flextronics. He gave one of the best keynote addresses I've heard in a long time. Among other things, he dismissed high-tech “phraseology” - particularly the venerable concept of Time to Market. He said the term has become “absolutely meaningless,” and yet he hasn't seen a presentation in years that doesn't include the phrase. He said if people were serious about achieving Time to Market, they would pay closer attention to the communication disconnect between the design environment and the manufacturing environment.

Brathwaite made a compelling case for a more thoroughly integrated inter-company and intra-company collaboration process where parametric, geometric, and supply-chain information are all dynamically linked from the project get-go - where the supply chain is set-up in parallel with the design phase so that the procurement people have a “heads-up” as the design process moves to completion.

After the keynote, I had a chance to meet a nice fellow in the Press Room named Fred Friedman from a company called Fabfile Systems. We stood looking out over the Exhibit Hall floor as he told me he's been to every PCB show for the past 12 years. “PCB West is the Number One show in the country,” he said. “This is the show that counts! You have board designers all across the semiconductor industry that started at this show. The industry sends their people here to refine their design skills and those designers move the industry. There's no way you're going to stimulate this industry without designers and their new designs.”

Friedman also said, “The industry has changed, budgets and motivation for attending this show have changed. It's very expensive when every booth needs a senior representative to present the thoughts of a company to the attendees. But, the fact that people have showed up at all this year is a testimonial to this show and to the companies who are here.” It was refreshing to talk to someone so determinedly optimistic about the future.

However, outside the Convention Center, Silicon Valley continues to seem like a bit of a ghost town these days - although there's a sort of serenity there as well. It's as if the people who are still up and running in the Valley plan to be there for the long, long haul. It's hard to walk down the quiet streets around the Convention Center, however, and not remember what a frantic and buzz-filled place this was at the height of the Boom. It was pretty crazy then - good crazy or bad crazy, who knows - but crazy nonetheless.

Interestingly enough, while PCB West 2003 was running at one end of the San Jose Convention Center, Synopsys was sponsoring the annual Silicon Valley Science and Technology Championship at the other end. A thousand (!!) middle school and high school kids brought in their science projects for the contest, along with their parents and teachers. When I walked past those crowds, they certainly seemed enthused and full of hope for the future. And maybe somebody out there was listening because, by the end of last week, NASDAQ had posted a one-day gain of close to 5%.

PCB Technology Leadership Awards and University Scholarship

Mentor Graphics Corp. was busy last week as well, announcing the winners of its 17th Annual PCB Technology Leadership Awards and University Scholarship at PCB West 2003. The competition is open to any design created with Mentor Graphics PCB tools. The company says that, this year, the program attracted a record number of submissions from many countries, including Portugal, Norway, Japan, Brazil, Singapore and Australia, as well as many universities.

Henry Potts, Vice President and General Manager, Systems Design Division at Mentor said, “Now in its 17th year, the program continues to attract the most skilled users of our PCB design tools.”

Industry experts judged entries in nine categories - Computer, Consumer Electronics & Peripherals, Portable Products, Data Communications, Industrial Control, Instrumentation, Security & Medical, Military & Aerospace, Telecommunications, University & Training Institutes, and Best Design Overall.

This year's winner for the Best Design Overall and Best Design for the Consumer Electronics & Peripherals category was Anna Pahoa, hardware designer for Kyocera Wireless Corp. Pahoa's entry was a flip cellular phone circuit card for the wireless communications industry. Pahoa studied drafting at the Golden West Junior College in Huntington Beach, CA, and has been drafting and designing boards since 1982.

Jonathan Andrews of Virginia Commonwealth University School of Engineering was selected as the winner in the University & Training Institutes category for his data acquisition system design prototype entry. He will receive a $2000 scholarship, which is co-sponsored by HP and is designed to promote innovation and excellence in education for PCB designers at colleges and universities.

This year's panel of judges included Andy Shaughnessy, Associate Editor of Printed Circuit Design Magazine, Mary Sugden, President of Copper Connection Inc., David Graff, Former President of the IPC Designers Council, Silicon Valley Chapter, Happy Holden, Manager of Advanced Technologies, Gary Ferrari, owner of Ferrari Technical Services, Inc., and David Graves, Vice President of UltraCAD Design, Inc.

Closing with a Taoist thought for the day, courtesy of Gary Smith

Effort and Destiny were arguing about who is the most powerful.

Destiny let fly an unending barrage of evidence to prove his superiority, concluding: “My dear Effort, if you are so effective, why don't you make hardworking people rich and give good people long life? And why are the intelligent unemployed and fools occupy important roles in government?”

Embarrassed, Effort admitted: “You are right, Destiny. Even when I seem to act, it is actually you who is acting.”

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-- Peggy Aycinena, EDACafe.com Contributing Editor.