From Glum to Glittering - February 09, 2004

It's a pretty bipolar world out there in EDA Land and it's just plain-long hard to figure out sometimes what's going on. Are we mad or are we glad? Are we bad or are we rad (as in cool). One minute, we're awash in the technicolor glow and glittering generalities of it all. The next minute, it's just a gritty grayscale of grim reality.

Whatever it is, it sure as heck makes you long for the middle ground sometimes. That rational, yeah-there-are-problems-but-that's-what-makes-it-all-interesting-and-we'll-make-progress-no-matter-what middle ground. The middle ground that lets you look forward to showing up at work each day to labor alongside your fellow journeymen. The middle ground where there's a spring in your step and a twinkle in your eye as you describe what it is you're doing and where you're trying to get to in the doing of it.

Which is why DesignCon 2004 in Santa Clara turned out to be a good place to be this week. There was glum. There was glittering. But there also was middle ground. Good, solid, hard-working, cheerful middle ground.

But first, a Letter to the Editor

Dear EDA Café,

I believe I may speak for many when I say that those of us that utilize EDA design tools are growing increasingly more concerned with the level of technical support we see from our EDA vendors.

I can open most any electronics related trade publication and see all the positive, sugar-coated sound bites that company executive staff are sharing, but when one watches their stock prices or has the opportunity to see first hand the level of support, or lack of, that they provide, one has to question where the truth lies.

The last time I recall our EDA vendor of choice paying us a visit was when our maintenance agreement was up for renewal. Otherwise, we increasingly find ourselves dealing with technical support representatives in far away time zones.

Have you ever tried to debug or understand a highly complex technical issue when the person on the other end of the phone is 12 hours away - our day, their night?

I would like to see an interview with perhaps the VP of customer support at Cadence, Mentor, or Synopsys, etc. Or better still, a question and answer forum with their customers.

I'll bet the customers would paint a much different picture than the vendors do.

Feel free to share my sentiments, but could I ask that you not include my name, as I still need to make a living in this industry. Besides I'm sure these EDA vendors are financial contributors to your publication.

I am certainly not out to lambaste anyone, but I do feel there is definitely a mismatch between message and reality.

Best regards,

Anon

Agitating for change

Richard Tobias is Vice President of the ASIC & Foundry Business Unit and the System LSI Group for Toshiba American Electronic Components, Inc. - a busy guy who's neither anonymous, nor apparently worried about having to make a living in this industry even if he does (regularly) put his name on a set of outspoken criticisms of his vendors in EDA Land.

Tobias moderated a Wednesday afternoon panel at DesignCon discussing the EDA Business Model. His panelists included Graham Bell from Nassda, Jacques Benkoski from Monterey Design Systems, Thomas Heydler from Barcelona Design, and Michael Buehler-Garcia from PDF Solutions. From the looks of things and the SRO audience, this was a hot topic. People on the floor and people on the panel were pretty animated. From that standpoint alone, it was darn good theater. Questions ran long and Tobias basically had to cut off the discussion just to clear the room for the next panel.

Standing in the hallway immediately afterwards, I asked him to summarize what he didn't like about the current models in EDA, why it was of any concern to him, why he didn't just buy the best tools from the most responsive vendors and get on with things, and what he felt would happen to those in EDA who failed to heed his warnings or those from others like him.

I think he might have been a little startled by my questions. After all, he is a big customer - why shouldn't he have a right (read “obligation”) to offer sage advice to his EDA brethren, people with whom he is on a first-name basis, people from whom he expects satisfaction.

Here's what he told me:

“The EDA business model is affecting the basic success of my business. They need to be creating the right tools to promote innovation in the semiconductor industry. The EDA industry needs to help us create better products.”

“I wear two hats in this discussion - someone who is in the market for good tools and someone who is discussing the economics of the situation. [Therefore], we are actively working with our EDA vendors [to move them forward]. There's a distinct link between the quality of the business models and the quality of the tools.”

“Cadence and Synopsys have business models that are geared towards what the financial markets want. What they should have are business models that are geared towards the profitability of their customers.”

“EDA vendors sell us tools for 3 years at a stretch, and then immediately forget to innovate around any of their [installed base]. You can buy a whole palette of tools from Cadence or Synopsys - everything from layout to simulation, synthesis, and place and route. But you end up not using a significant portion of those tools. You end up having to buy something from someone else instead to fill in the gaps where the tools you already own are inadequate. In my mind, if the EDA industry would have their business models more in tune with what we're doing in the semiconductor industry, we would all be better off.”

“Meanwhile, Cadence and Synopsys are falling behind. I ask you, why can't they be creative internally? Why do they have to go outside and buy innovation? Why isn't it happening in-house? Other big companies innovate - GE, for instance in the financial services area, or Intel in the networking and wireless areas. The big EDA vendors should be able to do the same.”

At that point the hallway was beginning to clear. People had clearly moved on to the next hour's program. But before he rushed off to his next event, I asked Tobias to suggest what would happen if his friends in EDA failed to heed his advice. Tobias was unequivocal. Either these guys clean up their act, or they're just not going to be around in a few years. Like I said, he's neither shy nor anonymous.

A well-delivered keynote

Tuesday's DesignCon keynote from Aart de Geus was great, as expected. The CEO of Synopsys has quite obviously mastered the art of public speaking, the art of getting the necessary and sufficient amount of data/slides/concepts into a 20-minute talk, and the art of the ad-lib.

He started by suggesting that DesignCon East, due up in April in Boston, would no doubt be more interesting because one could always hope that being in the New England Patriots' hometown meant that Janet Jackson might make an appearance. Per de Geus, such an appearance was guaranteed to be more interesting than anything a self-described techno-nerd could offer. From that point on, he had the sold-out crowd pretty much in the palm of his hand.

He proceeded to give an entertaining, historically substantiated, honest but upbeat, sincere but cautious keynote - something akin to a combination of Christmas Past, Present, and Future. He told us that the downturn in 1985 might have been bad, but this one is twice as long and twice as deep.

He told us that 2001 saw a 46% decline in the semiconductor industry and that 2002 saw a 32% decline. He said that downturn has led to unprecedented pressure on pricing structures. He said there's an orthogonal set of axes that include product differentiation, project scheduling, and cost, which can help us see where we've been and where we're going.

He reminded us that the move from 0.35 to 0.25 to 0.18 to 0.13 micron basically came off like clockwork. But that at 0.13, things got very, very sticky and there we remain. He said all of that was exacerbated by the far trickier move to 90 nanometers and the skyrocketing costs associated with 300mm fabs.

He said that design today is more expensive and more complex. He said the complexity was actually great news because there's more on-chip real estate. He also said complexity was actually terrible news because it brings on many more verification problems.

He said timing closure's not going away, power consumption issues aren't going away, signal integrity issues aren't going away, test issues aren't going away, and that all of this is leading to a confluence of DFM (that's “m” for “manufacturing”), DFY (that's “y” for “yield”), and DFE (for “everything”).

He said that in the first 30 years or so, computation was the driver - the killer app - for Moore's Law, or the result of Moore's Law. The next ten years, meaning the 90's, were driven by connectivity demands. Now, it's the consumer who's in the driver's seat. The consumer wants integration, low power, and low cost.

He said the sweet spot in design today is hovering at 5 million gates, and counting. He said users are asking, “How do I design high density chips?” And he reminded people that in the Age of SoC, re-spins are running at an average of 61% of whatever's coming off the line.

He said the Productivity Gap that everybody always laments is nothing new, has always been here, and will always continue to provide excellent motivation for EDA vendors to provide evolving tools that push the envelope.

He said new tools and new methodologies always go hand in hand. He said the move from rectangles to transistors to gates to macros to large macros to complete platforms is a natural evolution and one that's been assisted by developments from the folks in EDA.

He said that VHDL today has got about 40% of the users, Verilog's got about 60%. He said that all of the above combined means that we've got to have a language that can be used for both design and verification. He said that we should now and going forward be throwing our support to SystemVerilog - a language that's compatible with the principle HDLs in use today, and a language that can support many flavors of verification methodologies. He said that SystemVerilog is “a single formulation that will support a variety of formal verification techniques.”

He said, therefore, that DFV is here - that's “v” for “verification.”

He said using IP has been like playing roulette and that it's no surprise that people are often skittish because IP often comes with an unclear pedigree and unclear certification. He said applying constraint random testing is a superior way of rooting out nasty bugs - even in code that's already been proven viable.

He said that IP = DFV = IP = DFV.

His 20 minutes were almost up and so he closed with the question that every user needs to ask before launching into using any block of IP.

“Was the verification methodology used on that IP inferior to what I myself use?”

If the answer is yes, then it's thumbs down on that particular block.

“Was the verification methodology superior to what I myself use?”

If the answer is yes, then it's thumbs up.

Okay. It was upbeat. It was on time. Definitely the kind of the keynote address that people come from miles around to hear. Glittering and gracious and good.

A standing ovation

Finally, at least for this narrative, there was the Wednesday keynote address delivered by Tsugio Maimoto who serves as Corporate Advisor for Semiconductor Operations at Sony Corp. I was told by DesignCon organizers that Sony asked that this particular presentation not be taped (the rest of the conference was recorded), due to the proprietary nature of the presentation.

Interesting, because the talk ended with this 7-minute tape of The Little Robot that Could. This little guy had 80 sensors, a bushel-full of chips, and a mess of actuators. It could walk, dance, stagger backwards if pushed, shuffle forward if pushed, fall down, get up, flex its little fingers, swivel its head, react to the house beat, avoid objects, tilt its head endearingly, sing, and speak with emotion.

I mean, I ask you - who wouldn't be drawn to a little silver child-like being with bright black eyes that could dance a bit, sing a bit, and flirt shyly with the sweet young woman on the tape.

After all, isn't this every engineer's dream? To be able to dance a bit, sing a bit, and flirt shyly with a sweet young woman.

Not surprisingly, The Little Robot that Could got what was tantamount to a standing ovation from a room full of techno-nerds. A round of spontaneous applause.

Industry News - Tools and IP

Accelerated Technology (Embedded Systems Division of Mentor Graphics) announced support for the FR family of 32-bit RISC controllers from Fujitsu Microelectronics America, Inc. (FMA), beginning with the Nucleus PLUS real-time kernel support for the MB91301 microcontroller. The Nucleus PLUS kernel is the first commercial source code, no-royalty kernel support for the MB91301 microcontroller, giving embedded developers a royalty-free solution in which to build high-end applications in the automotive, industrial, communications, consumer electronics and computer peripherals markets.

"The Accelerated Technology Nucleus PLUS kernel provides vital support that helps deliver a complete and cost-effective solution to users of our FR microcontroller products, such as the MB91301," said Keith Horn, vice president of marketing for Fujitsu Microelectronics America. "This kind of real-time kernel support is an important factor in the growth of high-end MCUs into exciting, highly intelligent home equipment, automotive and communications designs."

Adveda B.V. announced its Univers product family (Unified Verification Solution) for both hardware and embedded software design of SOCs, including the company's flagship product Miss Univers (Marvelous Integrated System Simulator), which is a unified hardware/software co-verification tool. The company says Miss Univers performs combined hardware and software cycle-accurate simulations at 100 times the simulation speed of other co-verification solutions, while also providing unique debugging features.

Per the Press Release: “Hardware software co-design is a burgeoning area of leading edge SOC design. Current methods for hardware software co-verification involve connecting the Instruction Set Simulator and debugger with the hardware simulator by means of yet a third tool, resulting in three different simulation kernels. Miss Univers is the first unified hardware software co-verification solution with only one simulation kernel, directly steering RTL models and ISSs. This breakthrough technology eliminates the unwieldy integration overhead that engineers have historically faced both in terms of awkward data exchange and a loss of speed from the communication overhead.”

(Editor's note: One might wonder why they didn't go with Mr. Univers rather than Miss Univers. Perhaps they thought the Terminator would object.)

Altera Corp. announced that Cadence Design Systems, Mentor Graphics Corp., Synopsys, and Synplicity are partnering with Altera to deliver the “full benefits” of the Stratix II family, which Altera says is its newest high-density FPGA family, and the Quartus II version 4.0 design software. Per the Press Release: “The Stratix II FPGAs' new architecture is based on an innovative, new logic structure that is 25 percent more efficient, has double the density, and is 50 percent faster than the first-generation Stratix family.” Meanwhile, Altera's announcement came with endorsements from the all the big players in EDA.

Paul Estrada, Corporate Vice President for Market Development at Cadence, is quoted: “Stratix II customers using the Cadence Incisive verification platform can benefit from Cadence's new generation verification technology to compress total verification time by up to 50 percent, while teams using the Cadence Silicon-Package-Board design-in solution can reduce their time-to-market by eight to twelve weeks.”

Simon Bloch, General Manager of the Mentor Graphics FPGA design creation and synthesis division, is quoted as well: “Mentor continues its long-standing partnership with Altera on its new Stratix II device family. Mentor Graphics' complete FPGA flow with the Precision Synthesis product and the FPGA Advantage product provides advanced analysis, physical synthesis, and design optimization."

Rich Goldman, Vice President of Strategic Market Development at Synopsys, is also quoted: “Synopsys and Altera share a vision for complete design flows and continue to work together to realize the full scope of opportunities created by the Stratix II device family. The new range of design opportunities associated with higher capacity and higher performance FPGAs require 'ASIC- strength' design tools. A number of tools included in Synopsys' Galaxy Design and Discovery Verification Platforms, such as FPGA synthesis, PrimeTime, and VCS, have been proven through years of FPGA and ASIC design.”

Jeff Garrison, Director of FPGA Products at Synplicity, is quoted as well: “Synplicity and Altera have worked closely over the past year to provide superior support for Altera's new Stratix II device family. Our market-leading synthesis products perform special optimizations to take advantage of new features in Stratix II devices like the complex digital signal processing and memory blocks. We are excited to join Altera in servicing new market segments interested in these powerful new FPGAs.”

Ansoft Corp. announced a design flow using Ansoft's 3D electromagnetic tools for modeling and optimizing high-performance electronic designs that employ Xilinx Virtex-II Pro FPGAs. Per the Press Release: “FPGA platform solutions with high bandwidth DSP and Gigahertz-speed I/O place significant demands on PCB design. With the collaboration, Xilinx and Ansoft's joint customers can achieve multi-Gigabit speeds in their designs while using widely available, low-cost materials, connectors and PCBs.”

Suresh Subramaniam, Senior Design Engineer at Xilinx, is quoted: “In high-speed PCB design, it's astonishing how much extra performance you can obtain from off-the-shelf components when you optimize them with [Ansoft's] HFSS. With high-speed digital and analog RF components becoming more common in high-performance Xilinx PCB designs, using HFSS is necessary to assure the correct performance of the end design.”

Atrenta Inc. announced that Toshiba Corp. Semiconductor Co. has selected Atrenta's SpyGlass Predictive Analyzer to “enforce design reuse…because of its broad and deep range of RTL analysis functions, rich customization capabilities, the ability to easily deploy the industry's best design practices and reuse guidelines, and the most comprehensive support for the STARC rules. STARC (Semiconductor Technology Academic Research Center) is a consortium of eleven major Japanese semiconductor companies including Toshiba that has defined a set of guidelines for SoC and ASIC design and IP, which are emerging as the de-facto standard in Japan.”

Seiichi Nishio, Senior Manager for Methodology at Toshiba, is also quoted: “After careful and rigorous analysis of all available options, including all existing tools currently in use, we found SpyGlass to be the superior choice because it fully met all our requirements - powerful underlying technology, full support for STARC rules including mixed-language support, ability to easily customize rules using C and Perl, and the capability to effectively incorporate and deploy our own design rules.”

eInfochips Inc. announced that it has increased its use of Verisity's Verification Process Automation (VPA) tools. eInfochips says it was one of the earliest companies to “actively embrace” Verisity's eRM (e Reuse Methodology) and Coverage-Driven Verification (CDV) methodologies and is “one of the strongest advocates of e-based verification.”

Mentor Graphics Corp. announced it is providing Intel Corp. with drop-in core layout (DCL) kits for use with Mentor's Expedition PCB design flow for Intel's next-generation chipset, code-named Grantsdale. The companies say that the DCL kit will be available through Intel and will provide an Intel reference motherboard design, which integrates the CPU, chipset, and other motherboard components for use with the Expedition PCB design flow. The companies also announced that the DCL kit for Expedition will be available this year following the introduction of the new chipset by Intel.

Per the Press Release: “As microprocessor speeds continue to increase, it is becoming more complex to meet interconnect timing and signal integrity constraints while placing and routing the critical components, while also minimizing the number of layers and overall size of the PCB. Intel is addressing this challenge by providing a reference motherboard design in Mentor's Expedition design solution to its customers.”

Nassda Corp. announced that Aeluros, Inc. has adopted Nassda's HSIM hierarchical circuit simulator and analysis tool for verification of physical layer integrated circuits for the 10 Gigabit networking and storage marketplaces. Don Stark, Vice President of Engineering at Aeluros, is quoted in the Press Release: “We were looking for a solution that would allow us to simulate our sensitive clock and data recovery (CDR) circuits together with the large synthesized logic blocks that they drive. These simulations would have been prohibitively slow with SPICE, but the speed and accuracy of HSIM allowed us to verify our entire CDR system at once, ensuring that it met our power and speed goals.”

Prosilog SA announced the availability of the release 2.0 of its Magillem tool, the graphical generator of SoC platform. The company says that Magillem allows “an easy interconnection between different IP's with the AMBA, CoreConnect, VCI and OCP protocols. The IP Creator module generates an OCP or VCI wrapper which facilitates the interconnect of the IP to the targeted bus. The code generated for the complete system is VHDL, Verilog or SystemC. Moreover, as a native XML-based platform, Magillem is following the recommendations from the SPIRIT consortium. The Magillem 2.0 release is particularly important for System designers who want to build a complete transactional platform in SystemC at different levels of abstraction, and mix HDL and SystemC IP's. The verification challenges are also addressed with the availability of the eVC (e Virtual Component) OCP2.0 module.”

RF Engines Ltd. (RFEL) has leased a hardware/software demonstrator to one of the French Atomic Energy Commission Laboratories (Commissariat a l'Energie Atomique or CEA) in order to evaluate the PFT (Pipelined Frequency Transform) signal processing hardware architecture, in connection with their ongoing program of real time RF signal characterization.

Per the Press Release: “The work was carried out at a CEA facility just south of Paris. The main purpose of the work was to benchmark the use of the Pipelined Frequency Transform (PFT), one of RF Engines proprietary FPGA signal processing designs, for the analysis of very short duration incoming RF signals. The work focussed on pulse width measurement performance of the PFT, and assessed the performance of signal detection, acquisition, and tracking of signals down to 100-ns width, across a matrix of tracking speeds and durations. The RFEL development system used for the work incorporates a scaleable PFT with up to 1024 points running on four 1 million gate Xilinx Virtex E FPGAs, with performance data being displayed via RFELs proprietary software ASDS (Advanced Spectrum Display Software).”

Silicon Dimensions Inc. announced a new product, Chip2Nite, which the company describes as “a suite of tools that enables comprehensive design planning and analysis of complex hierarchical integrated circuits. For the first time, design teams have a platform that will enable logic designers and physical designers to use their combined expertise to rapidly complete block designs - resulting in reduced cost, lower risk and improved time to market. The Chip2Nite products directly address the difficulties encountered in current methodologies by enabling logic design engineers to contribute to design closure early in the development process. The wire centric technologies used throughout the product suite enable logic designers to rapidly model the resulting physical design. The use of multiple "what if" scenarios and analysis, for the first time, makes it possible for logic designers to produce designs that are near optimal for physical design closure.”

Rita Glover, EDA Industry Analyst and Consultant for EDA Today, is quoted in the Press Release: “Silicon Dimensions addresses one of the EDA market spaces where we see growth in 2004. With design starts at 130 nanometers and below rapidly increasing, design planning is becoming essential to avoiding design closure delays and development expense. Logic designers need to have tools that enable them to understand physical constraints to design efficiently and partner with the physical designer in the final closure process.”

Synopsys, Inc. announced that Toshiba Semiconductor Co. has licensed the rights, on a per-use basis, to use Synopsys' alternating phase-shift mask (PSM) technology for production of high-performance processors and logic chips. Toshiba says it expects to enter volume production at 65-nanometers using this technology in the first half of 2005. Per the Press Release: “In December 2002, Toshiba developed the CMOS5 65-nanometer production process technology, which offered 30-nanometer transistors and 180-nanometer pitches using 193-nanometer argon fluoride (ArF) lithography and PSM technology.”

Masakazu Kakumu, Technology Executive for Toshiba, is also quoted: “Our research and development qualification shows that Synopsys PSM technology enables us to increase our yields and control our chip performance at 65 nanometers by substantially improving the resolution of our existing lithography equipment. Having strong control over our lithography process is a critical component in meeting our yield goals for production on this difficult node.”

Triad Semiconductor Inc. announced it has purchased ViASIC Inc.'s ViaPATH software to design custom ICs that require only a single mask layer change for fabrication. Triad Semiconductor says it plans to fabricate the first chip using ViaPATH in Q1 2004.

Per the Press Release: “Sensor system developers typically connect an FPGA or microcontroller to mixed-signal products with heavy analog content. The ViaPATH structured ASIC routing software addresses the needs of these customers, who are currently using FPGA or common off-the-shelf processors and want an affordable custom IC.” Dan Wrappe, CEO of Triad Semiconductor, is quoted: “Using ViaPATH, we can quickly convert digital hardware descriptions to custom silicon that is interfaced to our mixed-signal ICs. The result is a cost-effective chip set. Combining ViaPATH with our core strength in mixed-signal technology allows us to continue to evolve products towards a complete sensor system on a single chip.”

Coming soon to a theater near you

FPGA 2004 - The twelfth annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays will be happening in Monterey, CA, from February 22nd to the 24th. Not surprisingly, sponsors include Altera, Xilinx, and Actel. There will be 24 papers and 42 poster presentations, with topics set to include new programmable architectures, CAD tools for programmable logic, rapid prototyping platforms, FPGA-based computing engines, and novel FPGA applications. ( http://fpga2004.ece.ubc.ca/)

Structured ASICs - LSI Logic and Synplicity are presenting a series of seminars - “The Platform ASIC Solution” - across a range of venues in North America in February and March. If you make it to FPGA 2004, you'll probably also want to get to one of these seminars as well - just for the sake of comparing and contrasting the technologies. ( www.synplicity.com/events/platformasic_solution_lsi.html)

Newsmakers

Adveda B.V. is opening its doors and has announced the “commencement of business as a software provider for the functional verification of both hardware and software, which merges the hardware and the software developments of a System-on-Chip (SOC) design.”

The new start-up is based in Eindhoven, The Netherlands, where Cor Schepens will serve as the company's CEO, Huub Erens is CFO, Henk Aerts is CTO, and Marc Seutter is Chief Architect of hardware tools. The company has also announced its flagship product this week, Miss Univers.

I had a chance to speak by phone with Cor Schepens on February 5th. He was speaking from his office in The Netherlands. Schepens is a well-spoken individual, at ease on both the technical and business sides of the start-up equation.

He told me: “We started with this idea a year ago. I knew that Henk Aerts was working on software tools, building a generator for fast ISS models. He had built a software debugger around that idea as well. It was great stuff and I thought it might be possible to build a company out of this. One or two weeks later, I thought of an old colleague who was working in his spare time on a hardware simulator. I thought, 'Hey - if we can combine this, we'll have a very unique offering.'”

“I checked with them and asked if they would be interested in making such a company, and we agreed. This process is exciting and exhausting at the same time, but we expect to see it paying off over time. At the moment, we're all working quite late each day getting ready for DATE and doing the things we need to do to get organized. We're busy building our tools and, technically speaking, we are ahead of schedule. But, business issues are time consuming and since we are not a big company, we are having to hire contractors to help with those things right now.”

“When we began, we knew we needed to find some financing, which can take a while. [Luckily], we found our business angel, who is now participating in the company, as well, in his spare time. Normally [people believe] that it is a lot easier to get funding for a start-up in the U.S. because Europe is a lot more conservative, especially in Holland. When you look for funding in Europe, people don't always know what EDA is and can't judge if they should take the risk [of investing]. I had one VC interested in us - one who did have knowledge of EDA - but they simply stated to us that they are investing [today] in companies that have already been out there for a few years. But they did say that they thought [our technology] was very interesting. It is easier to find venture capital in the U.S. where there is some awareness of EDA. [However], as we were about to get money from the U.S., we found our business angel here in Europe.”

“How did we come up with the name of the product? [Laughing] - We had another name earlier, Veronica for Verify Electronically. But the product provides unified verification, which was Univers, so we came up with Miss Univers.”

“There are lots of other companies with software debuggers or IDEs, integrated development environments. On the hardware side, there are some fast cycle-based RTL simulators, but the most used RTL simulators are still traditional event-driven simulators. Other companies are really making an interface tool. Mentor's Seamless is the main competition here and they are just an interface tool. You still need a software tool chain for a processor, plus you need your RTL simulator. The RTL simulator is really the bottleneck here if you're doing hardware/software co-simulation because it's running 1000x slower than the software part. Our cycle-based approach improves on that.”

“Our main [focus] is hardware/software co-verification. We've integrated the hardware and the software part, so right now if you look in that narrow band, we have no competition for this product. I believe hardware/software co-verification is a growing market. The RTL and software debug markets are mature now. That makes it all the more interesting for us, because in a growing market you can introduce a new tool a little faster.”

Apache Design Solutions Inc. announced a finalist in two categories for EDN Magazine's Innovator/Innovation Awards. The awards program honors outstanding electronic products and the engineers who invent them. EDN asks its audience of electronics engineers and managers to use an online ballot to select the final winners, although the magazine's editorial staff and Editorial Advisory Board also take part in determining the winners. Per the Press Release: “Apache's founding R&D team - Shen Lin, Norman Chang, Weize Xie, and Yu Liu - is one of four finalists, and the only EDA team in the 'Innovator of the Year' category. Apache's team is the first EDA team in seven years to be nominated in this category. Apache's RedHawk-SDL is one of four finalists in the 'EDA Physical Analysis' category.”

Cadence Design Systems and the 49ers Foundation announced that they have chosen the Children's Discovery Museum of San Jose as the 2004 beneficiary of the 11th Stars & Strikes fund-raiser. Cadence underwrites and organizes the Stars & Strikes bowling tournament, which features both Silicon Valley and celebrity bowlers raising funds for selected community programs. The goal of this year's event is to raise at least $500,000 for the Children's Discovery Museum. Proceeds from the event will aid in the construction of an 8,600 square-foot outdoor learning laboratory.

Virage Logic Corp. announced the appointment of Mike Seifert to the post of CFO for the company, responsible for all financial, administrative and operational aspects of the company, Seifert will report to President and CEO Adam Kablanian. Previously, Seifert was with Southwall Technologies, a manufacturer of thin-film coatings for electronic, automotive and architectural applications, SiteSmith, SmartDB Corp., Wayfarer Communications, PMC-Sierra, and Ernst & Young. Seifert has a B.S. in commerce, with a major in accounting from Santa Clara University.

Bits & Bytes

1 - Atmel offers solace after My Doom attack

Per the Press Release: “Atmel Corp. executives said that the company's Trusted Platform Module (TPM) ICs could help prevent identity theft, such as those perpetrated on Best Buy and PayPal customers last summer, as well as viruses and worms, such as MyDoom, Sobig.F and Blaster. In just one week, Blaster infected 500,000 computers and caused an estimated $1.3 billion in financial losses. Last week's MyDoom virus is reported to be the fastest spreading ever, infecting one in 12 PCs. Atmel's TPM chips provide secure hardware-based, storage and management of the user's identity, passwords, and encryption keys, unlike most software-only security solutions.”

Kerry Maletsky, Business Unit Director, North American ASIC/ASSP products at Atmel, is quoted in the Press Release: “The real issue with viruses, worms, and other Internet crime is identity. Can the identity of the data sender be reliably authenticated? Can the user or operating system determine that a program is safe to run, prior to its execution? With trusted computing platforms, the answer to both questions is yes, because the authentication and integrity of both the programs and machines can be absolutely verified. The only way to cheat the system would be to copy the contents of the TPM or physically remove the chip and put it in another system - activities that cause the chip to disable the system.”

“The concept of authenticated identity can be extended to the BIOS, operating system, and the catalog of registered programs to protect from worms and viruses such as MyDoom, Sobig.F or Blaster. In this context, registration is the process by which software is measured and said measurements are stored in a catalog of known measurements. Worms and viruses are computer programs. If a computer's BIOS and OS only allow execution of programs whose measurements match the values found in the measurement catalog protected by and authenticated by the TPM neither worms nor viruses could ever execute. Since the catalog of program measurement data is protected by the TPM IC, hackers could not alter it and go undetected. This capability could be particularly useful in preventing worms that invade servers through security holes and are difficult to detect until they have done a lot of damage. Unlike anti-virus software that can only be available after the virus has done some damage, TPMs offer the potential to prevent the outbreak before it happens.”

“TPMs can help prevent phishing and spoofing scams, as well. Last summer's Best Buy and PayPal Internet scams used 'spoofed' emails to elicit sensitive financial information from victims. Since TPM ICs can be used to ensure that emails are accepted only from 'authenticated' sources, including identification of the actual hardware generating the email, they could have prevented these crimes. If Best Buy, PayPal and the victims had used Atmel TPM enabled computers and servers, the thieves could have been foiled because the 'spoofs' that did not come from authenticated Best Buy or PayPal machines would have been recognized by the TPM hardware.”

2 - Low-k meets 90 nanometers twice over

Taiwan Semiconductor Manufacturing Co. (TSMC) announced that the company's low-k technology has entered mainstream production following the introduction today of ATI's Mobility RADEON 9700. TSMC says the introduction of the low-k graphics processor to the notebook PC market reaffirms the arrival of the low-k technology era. Per the Press Release: “Low-k technology improves device performance while reducing power consumption, making it an ideal choice for both high-performance and low-power applications. TSMC's low-k technology also offers design ease, which reduces overall design time due to a better power delay trade-off than that of FSG counterpart. This combination allows designers to take immediate advantage of TSMC's 0.13-micron and 90-nanometer Nexsys Technology for SoC design. The 90-nanometer Nexsys technology is the first process technology based entirely on low-k dielectrics, and is ramping to production this quarter."

Intel Corp. says it is delivering four new processors (formerly code-named Prescott) that are built on the company's high-volume 90-nanometer technology. Per the Press Release: “Intel's 90-nanometer process technology is the most advanced semiconductor manufacturing process in the industry, built exclusively on 300mm wafers. This new process combines high performance, low-power transistors, strained silicon, high-speed copper interconnects, and a new low-k dielectric material. This is the first time all of these technologies have been integrated into a single manufacturing process.”

3 - Ewald Detjens at Circuit Semantics

I also had a chance to speak for a few minutes by phone with Ewald Detjens, CEO at Circuit Semantics, Inc. on a rainy morning in late January. It was an interesting conversation as Detjens seemed both candid and down to earth. He was in his office in Mountain View, CA.

“Thanks for asking - people often think that my name is Dutch, but it's actually German. Things are going quite well here with the company. Currently, we've got 17 employees, all located in California. We're working with our customers to help them solve their leading-edge timing problems. Right now, people aren't willing to work with delays, so they're having to use large guardbanding to solve their problems. But as you go into deeper and deeper submicron design, the amount of guardbanding is growing, which means you'll often end up with pretty dismal timing numbers that are overly pessimistic.”

“We're finding that our customers are not willing to use large guardbanding - they want Spice-accurate timing numbers. For example, a cell will respond differently depending on the particular path. There's a specific rise time at input and that's contextual. We can figure out exactly what that response is given the exact layout information - and we can do it accurately.”

“A lot of SoCs are still running in the range of a couple hundred megahertz. But our users are beyond that, often having designs running at more than a gigahertz. It may be more work to use our tools, but if you're bringing out a new microprocessor and there's a lot of competition, [you may have no choice]. People are really pushing aggressive design and analysis techniques, and then they're worrying about power and noise. These are very real problems there today - we've done some work in the noise characterization sphere and plan to do more this year.”

“Timing closure today is a horrific problem. For someone who's done a design and has timing violations, our software doesn't tell how to solve the problem - but our software will tell you exactly where your are. For someone who has a problem and has done a lot of guardbanding, we can provide a highly accurate report. We allow people to go back and alter their designs, all the way from the start through to place and route.”

“Our interaction with customers tends to be pretty detailed. It takes a long time for them to evaluate our tools, and they may have some very specific technical issues. They might have a new style of circuit design or perhaps they're using a different set of EDA tools. There's certainly a lot of mix and match going on out there, even today, so during an evaluation we're making sure that all of the tools work together.”

“We need to be able to work with many different tools, so we're partnering with many people. We're part of programs at Synopsys, Cadence, and Mentor. However, a lot of our customers tend to have in-house tools, as well. EDA companies give good overall solutions for the pack, but leading edge people have large in-house CAD tools that are specific to their type of technology.”

“So, sometimes we sell consulting services, sometimes we do tools evaluations, sometimes we just sell tools. We're actually hiring right now and actively looking for people who have EDA backgrounds, programmers largely. We need programmers with a background in circuit design. The average EDA coder doesn't really understand circuit design. We need people with experience in graph matching, people who can work on state timing analysis, people who understand how the circuit works. It used to be, in the early days of EDA, that all of the synthesis people used to be circuit simulation people. My first work was in circuit simulation, and then I got into synthesis. The whole trend [over time] has been to abstract away from the transistor to the gate level [and beyond]. [That may be one reason for increased hiring in India.] I'm being told that the universities there are giving a broader background to their students.”

“EDA was definitely on a gravy train for a while with the dot.com bubble, but last year was a bad year for EDA - the customers were really pinched. We saw some customers going out of business. There was a tightening of the budget for EDA tools and people were asked to limp along. Between last quarter and this year, however, we may be seeing some [improvement], or maybe we've just gotten used to this new world. [In any case], maybe I'm a masochist because I believe there are still many interesting problems in EDA and I continue to enjoy being involved in the technology as it evolves.”

In the category of …

Blame it on Microsoft

Several in the EDA Business Model panel at DesignCon addressed the idea that EDA vendors should link their revenues to the success of the product that is designed using their tools. Afterwards, a software guy told me that he is somewhat troubled by this idea.

“If EDA vendors don't make money off of their tools unless their customers produce successful design or good products, isn't that the same as somebody telling Microsoft that they won't pay them for the use of Word unless what they write using Word is successful or good. That's just nonsense. Microsoft sells you Word and you're the one responsible for the quality of what your produce with it. That's not Microsoft's responsibility.”

“EDA tools are obviously more sophisticated than Word, but they don't provide the lion's share of the innovation and creativity in the end product. That's the responsibility of the customer.”

“Another analogy would be that a good programmer has to pay more for the use of a programming IDE than a bad programmer. Again, that's just nonsense. This doesn't take away from the importance of having high-quality design tools, but the burden still remains on the user to do good things with good tools.”

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-- Peggy Aycinena, EDACafe.com Contributing Editor.