Date:      Thursday, October 13, 2011

Time:      11:00 am - 12:00 pm PDT (US)        

Click here to Register. 

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Date:      Thursday, October 13, 2011

Time:      3:00 pm - 4:00 pm CET (Europe)

Click here to Register.

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Abstract:
Virtual platforms play a significant role in system level development, but require integration with ultra-fast emulation systems for HW/SW co-verification.  In this webinar we will introduce the new integration of Aldec's Transaction Level Emulation System with Imperas' OVPsim virtual platform simulator.  Hardware and software design teams are now able to implement virtual models of processors, memory and peripheral modules while the RTL modules run in the emulator board.  This integration provides a high performance solution, ideal for early HW/SW co-development and architectural exploration.

Agenda

• Virtual Platforms: What are the benefits?

• SoC Design Flow with Virtual Platforms

• Imperas’ OVP and OVPsim

• TLM 2.0 Interface

• Integration of Aldec’s Emulation System with OVP and OVPsim

• Processor Debugging, Memory Debugging, Hardware Debugging

• Live Demonstration 

Presenters:

Louie de Luna, Aldec Product Manager

Larry Lapides, Imperas VP Sales

Piotr Czak, Applications Engineer

Time not fit your Schedule or Time Zone?

We invite you to proceed with registration. Following the Webinar, all registrants are emailed a link to download the recorded Webinar Presentation to view at their convenience.

To register or view more Aldec Events, please visit http://www.aldec.com/events.