Introduction
Given today’s economic picture, I am sure everyone in EDA is thinking about and perhaps worrying about the future of EDA.
The national economy for the last several years had been driven by the consumer segment. Consumers were very confident in their own financial positions buoyed by the rising value of their greatest asset, namely their home. Many took out home equity loans to fund purchases of non-essentials. Now that the housing market is in free fall and now that credit of all kinds has dried up, consumers have backed off their spending spree as reflected in the drop in retail and automotive sales. With large layoffs being announced frequently, people are justifiably concerned about their own job security and there is general uncertainty about the state of the economy.
In recent years the semiconductor industry also has been driven by the consumer electronic segment which includes products like cell phones, home entertainment systems, and computers. The drop in sales of these consumer items impacts the firms manufacturing chips and in turn the EDA firms who supply them tools.
A few data points:
Nokia the global leader in cell phones reported fourth quarter revenue down 19% year-over-year. Nokia CEO OLLI-PEKKA KALLASVUO said "In recent weeks, the macroeconomic environment has deteriorated rapidly, with even weaker consumer confidence, unprecedented currency volatility and credit tightness continuing to impact the mobile communications industry”.
On February 26th Dell Inc. reported results for the fourth quarter and the entire year for fiscal 2009. Total revenue was $13.4 billion, down 16 from the fourth quarter of the year before. Revenue for the year at $61 billion was flat compared to fiscal 2008. Dell press release noted that “Dell first identified slowing IT-industry spending in the U.S. a year ago. Deferred spending has increased and spread worldwide, significantly affecting overall fourth quarter demand across all regions and customer segments.” The company had previously announced $3 billion in planned cost reductions by the end of fiscal 2011.
Intel reported fourth quarter revenue of $8.2 billion down 23% year-over-year and 19% sequentially. Die to economic uncertainty and limited visibility Intel did not provide a revenue outlook for the next quarter but for internal purposes is planning revenue in the vicinity of $7 billion compares to $9.7 billion in the first quarter of 2008.
TSMC reported fourth quarter revenue decreased 31% year-over-year and 30.6% sequentially. The firm expects revenue in the first quarter to be in the range of NT32 billion to NT35 billion compared to NT87 billion in the first quarter of 2008. January sales were down 59% from January 2008 and 5.5% from December. Lora Ho, VP and Chief Financial Officer of TSMC, said “The global economic recession continues to worsen. Fourth quarter end-market sell-through was much below the already conservative expectations, and consumer demand remains very weak. This has led to a rising DOI for our customers, who continue to pare their inventories aggressively, resulting in a further significant cut back of wafer demand.”
On February 25th research firm Gartner forecast that the global semiconductor revenue would fall by 24% to $194.5 in 2009. In mid-December, the firm had predicted a 16% drop. Bryan Lewis, research vice president at Gartner, said in a statement "We believe that the financial crisis has reset the semiconductor market. After the 2001 recession, in which semiconductor sales plummeted by a record 32.5 percent, semiconductor sales took about four years to get back to 2000 levels." Gartner forecasts the semiconductor industry would return to growth in 2010, but reach its 2008 level only in 2013.
Despite this gloom and doom environment, several of the EDA executives that I have interviewed in recent months have expressed confidence that at least their companies were well positioned to capitalize on the situation. From the “glass is half full” perspective, they saw an opportunity to market and sell products that offered substantial increase in productivity to firms under pressure to reduce cost and accelerate time-to-market.
I had an opportunity to talk to a man who has held executive positions at three EDA firms including being the CEO of one of the Big Three. Today, he heads a fabless semiconductor company. From that position, he has a front row seat to view the EDA and semiconductor industries. I spoke with him about his company, his business model and the state and future of EDA and the semiconductor industries. The man is Jack Harding.
Jack, would you give us a brief biography?
I went to Drew University in Madison, New Jersey and majored in Chemistry and Economics. Then I went to Stern School at NYU. From there I went right in to intern at International Business Machine in a sales function. I sort of stumbled into technology and never left. I worked at IBM for several years as a sales guy. I had a distinguished career there: Rookie of the Year for the company. I did well there. Then I recognized that it was going to take me 25 years to become a vice president. I decided that this wasn’t for me. So I went to a startup called ZyCad in the EDA business, where a couple of ex-IBM’ers had been working in the sales organization. I was employee number 20 in that organization. That went public in the summer of ’84. I stayed there for 10 years. I went to Cooper & Chen Technology here in California as CEO. I took that firm public about a year later. I sold 10% of the company to Synopsys and then six months later sold the entire company to Cadence. I worked for Cadence for a year, organized the firm into business units that reported to me. After a year there I became CEO. I left there in ’99 after three years. I started eSilicon 9 years ago this coming March 1st.
How big a company was Cooper & Chen when Cadence took it over?
Interestingly enough there was a couple of metrics. We were doing only about $15 million but they bought the company for $500 million. Thanks to Synopsys, they got pushed into litigation by the FTC. While we were getting through the FTC, the Cadence stock had doubled over the seven months. We had no collar on the deal. That is there was no limitation on whether the stock went up or down. By the time the company was acquired, we received $1 billion in valuation for $15 million in revenue. What is amazing is that few people know about that. The employees owned 100% of the company. There were no venture capitalists involved. When we went public, we sold 15% of the company. So they got a very good deal. But the other 85% was owned by the employees. So the deal while spectacular did not hit the radar of the financial community because you didn’t have VCs out there pounding their chest about how smart they were. Prior to the dot.com period, this was probably the grandest transaction ever heard of in Silicon Valley before the crazies of ’98 and ’99. It was good times for Cooper & Chen.
You were at Cadence for about one year, when you took over as CEO. Cooper & Chen was a $15 million company. How big was Cadence at the time?
When I got there, it was $1 billion. We had just crossed over the $1 billion under Joe Costello’s leadership. When I left there, I believe we did $1.5 billion. The proudest statistic to report is that the value of the company was never higher, prior or since. The market cap of Cadence was just under $10 billion. Of course, today it is $1 billion. It never came close to that again. We did very well there. We grew well. Profitability was outstanding and expanding. We were actually growing the pie as it were.
What was it like going from being the CEO of a $15 million firm to becoming the CEO of a $1 billion company following the legendary Joe Costello?
There are two pieces to that. One was the size and one was the Costello factor. Following Joe was a delight. I had known him for the previous 10 years. We had always compared notes about where EDA was, where it would be one day and what would it take to be successful. When I got into Cadence, he and I were seeing eye-to-eye on things. Not the least of which was that EDA had to be more than just a tool supplier, just a tax on the semiconductor supply chain. We both felt very strongly that what has now become the fabless ASIC model was the future of EDA. We had different perspectives as to what degree that would be the case. But we both agreed that EDA’s existence was going to run into the wall that it has hit for the last 10 years, zero growth. Since we had very complementary and symbiotic view of the future of EDA and what should be the strategy for Cadence, it was a delight working with him. I valued his creativity and enthusiasm greatly. On the dimension of size when I took over, in one sense - I am not trying to trivialize it – it was more of the same for me, because I have always done my best work thinking about these problems conceptually, in levels of abstraction. Cadence just gave me more opportunity to think about the EDA market on a long term, strategic basis and about where Cadence should be positioned. I greatly enjoyed having the resource at my disposal to execute those plans to change and evolve the business. For me it was not a different thought process which is the big risk and what it takes to go from small to large. You go from managing nickel and dimes one day to the strategy the next day. I always thought in strategic terms and had excellent people doing a lot of the execution for me, even in smaller firms. Cadence was just a better fit platform for someone with my business style.
Then you had the opposite experience, going from a $1 billion company to a startup. Did you go directly to eSilicon or was there a hiatus in between?
When I left Cadence, I had never before planned a career move. I got recruited here or acquired there or something like that. For the first time in my adult life, I stopped and said “What do I want?” I took about 9 months during the ’99 dot.com frenzy. I ran around looking at different businesses in the dot.com area and frankly concluded on a contrarian basis that companies without revenue would not survive, no matter how sexy there were. I sort of lost interest in a lot of those Internet 1.0 concepts. I started up eSilicon as the confluence of what my experience was, of what industry experience and knowledge I had and also what I thought was going to be the fundamental trends in the semiconductor business going forward. We started the business at the time with a sort of Internet veneer but we rapidly jettisoned that to make it more of an Internet core for the operational functions where it belongs and went back to basics around that we were going to sell chips and make money. The company just took its life from there. It was the right trend at the right time, even though like everyone else we have been dealt the setback of the dot.bom and now our current recession. We have been able to navigate around the traditional semiconductor industry and have a very viable business that has got great prospects.
Would you tell us some more about eSilicon?
As we discussed we started the business in March 200. It has been the fastest 9 years of my life. I’ve very mixed emotions to say. The company is a dedicated fabless company. We do not do this to fill empty capacity in another country. We do this because we want to make custom chips for the benefit of OEMs and the fabless semiconductor industry. About half of our companies are name brand public firms, one half are private firms. In another dimension about one-half of our companies are system houses and one-half are semiconductor industry firms. If you think abut X and Y axes, we have a very broad portfolio of market segments from a wide variety of companies from a dozen countries and multiple continents. We sort of think of our company in financial terms as a mutual fund of semiconductor opportunities as opposed to the traditional single share of stock. Inherent in that portfolio is a balance and a risk mitigation factor that allows us to weather the uncertainties of markets as they ebb and flow whether seasonally or secularly as things go in and out of favor. For example, we don’t have a large concentration in consumer products because it is just too damn risky. That strategy is paying dividends right now while the consumer markets have just basically gone to zero. That’s sort of the backdrop. We are spread around the world. We have an office in Sunnyvale. We have designers and technologists on the east coast in Allentown, Pennsylvania which is in the shadow of the old Bell Labs facility and also inn Murray Hill. There are 30 people in Bucharest Romania, digital designers as well as packaging designers and other infrastructure jobs. We have a package and assembly office in Shanghai and a sales office in Japan. As a small company we are globally positioned. The theory behind that is not so much to chase low cost centers. That is really not our goal, because the class of chip we work on requires local support. We are making 65 nm chips right now with over one billion transistors in them and our customers want to know that our engineers relevant to their product are generally in the same time zone. So we have positioned our teams accordingly.
Were these locations the result of acquisition or did you simply decide to go to Romania?
With the exception of Romania, everything opened by us was strategic. In Romania we bought a small business there 4 or 5 years ago with maybe a half-dozen people. We built that up to abut 30 folks now. It has been very successful. The 30 folks are highly educated. Their English skills are excellent. They are in complementary time zones to our customer base. The retention is virtually 100% as compared to India where there is 30% turnover very year. Any you can drink the water in Romania.
Just in terms of the volume, we make relatively large chips. We are shipping just under 10 million units per year. So there is a fairly large volume of parts running through the company. That of course, endears us to the supply chain. It is worth pausing for a second on the relationship with the supply chain. We have to talk about what we do for our customer some more. But for our suppliers, the relationship is very interesting. We are in effect a channel for them. Our wafer suppliers like to make wafers. That’s what TSMC likes to do. Our package and test guys like to make packages. What they do not like to do, if you talk to them privately, is call upon every little company and every little project in big companies around the world seeing if there is an opportunity for them. They have their hands full with the huge corporations that are shifting from the IDM model to the fabless model. It is all they can do to keep up with the demand of the likes of Philips and STmicro. What we provide them is the triage of the market to find the next iPod chip or the next red hot application that might run huge volumes. In the meantime, to the extent that we are making chips that have lower volumes than they would be interested in individually, we are bundling them up in a way that they just have to deal with one company, namely us, to get all the information they need to build these chips. There is inherent efficiency there that translates into lower costs for us to pass on to our customers or share in to generate our own margin. That is a very important aspect of our business model that we create our own margin by working with the supply chain. We aggregate a lot of demand, so we buy less than 90% of customers can individually number one and number 2 the inherent efficiency of giving them access to the market without them expending sales and marketing dollars gives our supply chain the added incentive to give us lower costs. So we create margin from these business conditions. Technically speaking, we also create margin, since we make a couple of dozen chips per year, we are constantly improving the methodology to have smaller dies and higher yields. Both of those variables are integral to the calculus around the economics of semiconductor. We just believe in general that we (and our customers believe it too) can make a smaller chip and a higher yielding chip than they can thereby once again creating margin that we can share. The business model early on had been accused of being a margin stacking function. In fact, we are a cost reducing function and have a standing offer to any chip company in the world that we will deliver them their chips at their costs today and we will do all the work and still make money. In other words, they can let go of all their infrastructure, all the fixed costs they have and we will deliver their chips to them at their costs and make money. That has been the business model that has evolved over the last 9 years.
We launch about one new design or product into the market per month with our customer’s logo on it. It is a good flow of business. Five years ago that would not have sounded like so much. I was just talking to Handle Jones of IBS, the consulting firm. From memory he told me that in the year 2010 only 8 companies in the world will tapeout 8 or more 65nm parts. We will be one of them. The people we are in company with are the names like Qualcomm, Broadcom, Samsung, and TI. The people you would expect. That shows you a couple of things. The number of design starts is shrinking due to the integration of multiple chips, a more cost effective and a more powerful solution. Number two, the logical extension of this obvious trend is that your average chip company will not be making very many chips in the future. Therefore, they won’t be very good at it. An integral part of our value and our future success is linked to the fact that your average opps teams will be making one chip every 18 months at 65nm. That simply does not justify keeping them on the payroll. Just like EDA went from 100 companies writing their own EDA tools in 1982 and 1983, that reduced down to 3 or 4 companies by 1986. The same thing is going to happen here. Unless you’re IBM, you can not justify an internal opps team, no more than you can justify your own mergers and acquisition team on the payroll. It simply does not make sense. The economies don’t support it but more important, if you are making one chip every 12 to 18 months, you can not be good at it. We are confidently predicting the jettison of the last major chunk of the semiconductor industry which is the physical design, operations function into multi billion dollar industry, just as EDA, wafer, package, test and IP have become multi-billion sub-industries. Operations which is about a billion dollar industry today will become a $10 billion industry in 3 to 5 years.
The key message is “Do it your self is dead”. You would not go to your board and say “Great news. We are going to write a new Place and Route tool”. The same thing will happen in the next few years, particularly with this recession. Your average CEO will not walk in and say “Let me tell you how I am going to buy a bunch of EDA tools, have 10 physical designers, and hire my own opps team in order to do that chip every 18 months.” It will not happen. We are getting calls on a weekly basis from companies that are recognizing this and are looking to shut down their so-called backend function and outsource it to companies like ours. Not just us but companies like us. It is a very exciting time for this business model.
The trend is a change in the compound growth rate of the semiconductor industry. Over the last 35 years. What you can see is that every time there has been a drop or a recession in the semiconductor industry, some major chunk of that infrastructure has been jettisoned and formed into a new subindustry.
 |
We launched what a lot of people thought was a crazy model 10 years ago. In many respects it was an extension of a vision I had at Cadence that was unfulfilled. Today it is a $1 billion market segment that is growing 3 times faster than the semiconductor industry during good times. It is understood to be the model of choice for not only small businesses like ours but all the large companies have morphed into the fabless ASIC model underscoring its value and importance. Specifically, our company is enjoying profitable growth and we are expecting a very bright future and absent a global recession I think we would be talking about very bold growth in the immediate year. Our expectation for the year 2009 is to be flat over last year which was profitable and outstanding. We are delighted with that candidly. If we can maintain flat growth year-over-year, we feel we have done our job.
What was your revenue last year?
Just about $70 million and we were profitable.
We surveyed customers that elected not to do it themselves and asked “Why did you make this decision?” The chart below is an average or a proxy for their analysis. If you notice, it says that eSilicon has 10% higher COGS. They all presumed that we would cost more even though we don’t. But even when they said “We guessed that you might be more money, but the savings were so compelling that we decided we don’t want to do this anymore.”
 |
When someone outsource whether an individual going to a doctor, a lawyer or tax advisor or where a company goes outside, sometimes it is because they flat out lack the expertise, sometimes they have the expertise but not in sufficient quantity to do everything they need or want to do at a point in time, sometimes they do it for cost savings and sometimes they think that someone else can do a better job. It sounds to me that your pitch is a combination of the last two that is that you can do a better job for less money.
Yeah, but you know what I will tell you is that in the last 30 days two of the top 10 largest semiconductor companies in the world signed contracts with us to make chips for them. For the first one, the case was one of peak load. They needed more chip capability and did not want to hire with fixed costs at this time. So honestly five years ago I would not have predicted that outcome but we are seeing it more and more. The big guys are saying “No more fixed costs. If we need the chip at the margin, if they can make 10 chips but need 11 chips, we will outsource the 11th.” It is that category as well. That is what is driving the top brands, the top 10 guys, to work with our model.
Other than large companies that have their own internal operations, are there any firms like eSilicon out there?
Yes, there are a few. There are two companies that are closely held by the two large fabs. TSMC owns 50% of a company called Global Unichip, which has a version of our business. What is different about them is that they do lots of pass through distribution sales. In other words, they might work in remote territories and just service the account by selling them wafers with a small markup. But they also do some of what we do. That’s one version. Then USMC has a company called Faraday which has a similar model to GUC. It has large ownership by USMC and they are tightly coupled at the hip. There is a third company that looks like us and is independent call Open-Silicon. But I think that they have a large percentage of their employees in India. Basically they are chasing the low cost model as opposed to the complexity model. Our customers want to make complex chips that have to last for 5 to 10 years in systems reliably with very high standards. We have fewer customers that put chips into toys that are disposable. Between the four companies there is something lie a half-billion in revenue. The there are dogs and cats all over the place that used to be design companies that now “tape out” They are still design centric. Ninety percent of their revenue is design. The vast majority of our revenue is from production. We are a semiconductor company that happens to design as necessary, when our customers need us to do physical design and layout. But we make money shipping silicon.
You website describes engagement solutions which differ by where in the design flow eSilicon takes over; netlist, GDS II, custom, .. Would you expand on that and give us some idea of the percentage of the business that comes from each?
There are really three broad places with some subcategories. The most common is the netlist handoff. That is where the customer says “I’ve finished the RTL, I may or may not have done synthesis yet but I am right about the time that the netlist is done.” About 60% of the time we get a netlist and we do the physical design, we do the layout. Then you move back to the front of the design process, where there is a specification handoff. This occurs about 5% of the time. This is based upon our own limiting factors. We don’t like this as much but every now and then we will do a spec handoff. We will write the RTL. It has to do with the application or the customer. If it is an existing customer, who wants us to help them out, we will do it. That’s about 5% of the time. Then about 35% of the time, there is the so-called GDSII handoff. That’s where the physical design is done, the tapeout is now ready to be prepared and launched to TSMC and we take over the flow right then and there. What they all have in common is that we always make the silicon, even though it has the customer’s name and logo on it. We always make the chip. We earn money by shipping chips to them. The reason we can do that is that we believe we can manage the yield even, if we did not do the layout. We can manage the yield with our team of experts, who are here full time, doing it every day. We are better than our average customer and we run those chips until the end of life. In some cases it is 3 years and in some cases it is 10 years. As a nine year old company, we have customers now who have been shipping silicon for 6 to 7 years with no end in sight. It could be industrial chips, networking parts. Things like that. These are the three basic models. That is pretty much true with all our competitors.
To what extent do you need to use the same tools as your customers? How do the design flows dovetail?
In a GDSII handoff, we do not care what they use. A GDSII file is a GDSII file and everyone converges there. If it is a netlist handoff, the bulk of our work is done with Magma tools. There is no reason that a chip that was designed with front tools from Synopsys or Cadence can not be laid out with tools from Magma. So that’s not a problem. If we do the spec handoff, which is rare, we define the tool flow, so there is no issue by definition. The flows that we work through do not have a bearing on our interface to the customer. The handoffs are at logical points where you can make tool changes. Obviously, if our customer did half of the layout with Cadence tools and asked us to finish it with Magma tools that would be a non-starter. There are fortunately logical places in the methodology that we use, standard methodology in the industry, which allows these things to happen very gracefully.
Do you have any proprietary tools that give you an advantage or is it a matter of standard tools used by people with greater expertise?
We do not make EDA tools at all. Where we do spend a fair bit of time and money is in writing scripts and infrastructure that automates the tools further. We do not want to be in the business of writing tool shells around EDA products or writing that interface to EDA products. What we do is write sophisticated shells that let the methodology run without human intervention and as fast as possible. From an EDA perspective, we look much like a large IDM would in terms of facilitating the EDA purchases they have made and staying away from polluting or contaminating those tools with home grown code, which I can tell you with some level of expertise, is a mistake. Having said that, we have an in-house software development team. What they write is infrastructure tools. In the last nine years we have built and patented on many different occasions an internal methodology or infrastructure we call eSilicon Enterprise. Basically, what we have done is to write a semiconductor business-to-business, a business application B2B – there was a time we would have been embarrassed to say that – that sits on top of an Oracle ERP and production control system. What that allows us to do is to manage dozens of chips electronically with very little human intervention and virtually no error. We have spent a fortune developing tools that purge errata out of the database from our supply chain which we access automatically, purge out the mistakes and post them to an Oracle database which we didn’t see any reason to reinvent. Then we publish that with our own tools back to the Internet so our employees and our customers watch the production occur in virtually real time and capture any delays or shortcomings immediately. So our customers don’t wait for our sales guys to come back from vacation to find out where their chips are. They can log on and see that they are at metal level 4 and moving to metal level 5 in 12 hours. The same is true for delivery schedules. What’s been ordered, what’s been backordered? That is done electronically and allows us to have many, many fewer people and offer a much higher quality of service to customers and allow us to achieve every transaction for every chip. If you think about it, our worst performing chip is still someone else’s baby. So we might not be so excited about keeping track of the details of a poorly performing chip but we do it anyway because it is critical to our customers. Anyone who has tried to run a business like us with spreadsheets and Microsoft is not getting it. It is just impossible.
How do you charge for your service?
We have two places where invoicing takes place. One is the non-recurring engineering where people say “Please do the physical design. Can you get the test program written, the mask. etc? Can you get this ready for production? For a 65nm chip that runs from $2 million to $3 million. And we make the bulk of our money shipping silicon. We make a chip that has cost x and we bill it to you for y. The delta is our gross profit. The interesting thing is that while our customers are always looking to have lower cost - they are always under pressure too – we can point to their collective rationality: “Why engage with us, if we are not cheaper than you can do it yourself? We have not fooled 100 customers. They are smart people. The same spreadsheets we have. We make a chip for them of super high quality at a price point less than or equal to what they could do. The rate at which we sign up new customers is testimony to that factor.
In dollars per wafer or per chip, is it cost plus?
It is not cost plus. Over the years there have been a few cost plus situations where it was unique and warranted. But generally speaking, we quote a price to a customer. We guarantee that price. We typically guarantee them two, three or four price breaks in terms of time and volume. And we take the yield risk. Our customer can know that they can acquire that part hell or high water for the price we quoted them as opposed to a promise from the opps team. And if the opps team guys are wrong, what do they do? It costs more. It is that simple. By the way, they are never right. They turf a lot of the cost over to R&D and Marketing and to everywhere but the COGS or the chip. What happens is that the CEO or CFO says “Those things didn’t cost us $9, they cost $12 when I add it all up.” Where do you go? In our case, if we quote $19 and heaven forbid it costs $11, then we eat that. So our customers know absolutely, positively that they are not paying us more for that part than what we quoted them in the timeframe we quoted it. There’s a great value in there. There is a great risk mitigation factor that executives understand. The operations people do not.
In January 2008 eSilicon acquired SwitchCore’s product lines. How does that fit in to eSilicon strategy?
SwitchCore was a unique case, an atypical acquisition. It was a company that had missed a generation or two of new products and yet they had a couple of products in the market shipping successfully. Due to the direction of their Board, they elected to get rid of their semiconductor business. So they sold us the product lines and we continue to service their customer installed base. We do not seek new design wins. We don’t do anything to support the product, only supply chain continuity. It is order fulfillment. We acquired those product lines. We do have any op expense or R&D around them. The customers, by the way, are delighted. We are an ongoing entity that is happy to supply them, whereas they were buying the chips from a company that was winding down and going out of business. The customer is happy. We are happy. We are selling chips with no op expense except the margin. The company was happy. They got a soft landing for something that wanted to shut down. Candidly, we are getting a lot of these calls now. There is a lot of small to medium sized companies that are sort of the walking wounded. They don’t have good prospects. Their cash balances are waiting yet they have products they have been shipping for two, three or four years to customers in industries that will have demand for 10 to 12 years. We are in conversations with a lot of folks who are looking to arrange a transaction whereby we take them out of that situation and compensate them today. They get a soft landing and their customers are happy.
You have said a lot about the way people will be doing semiconductor production in the future. Smaller companies will look to outsource because they can’t support the fixed cost of maintaining operations. How does this impact the future of EDA vendors?
I think that EDA is in a world of hurt. The business has been flat for 10 years. It is the only member of the semiconductor supply chain that gets paid regardless of success. Everyone else shares in the success of the production or in the failure of the production. Even IP, that takes an upfront fee, gets compensated in large measure on royalties based on volume shipments. There is that one mini exception. But everyone else lives and dies on the same side of the table as the firm making the chip except for EDA. The market place has simply rejected that. The irony from my perspective is that few industries add more value to the world than EDA. With no EDA, there is no semiconductor industry. With no semiconductor industry, there is no IP infrastructure. This is a trillion dollar industry driven off a $4 billion market segment because their business model is broken. Until they start to accept the risk of production in one form or another, they will always be relegated to a tax and therefore not appreciated or valued. You take that background, you add your point that the number of design starts is shrinking every single year and they are being aggregated into companies like mine. Who do they sell to and for what? If you are going to do one 65nm chip or one 45nm chip a year, how many tools do you need? If those products are being rapidly deployed and outsourced to fabless ASIC companies like mine, I have all the tools I need. I am not going to buy more. What does EDA do other than fight over the existing shrinking market which is what they are doing today? They are a world of hurt.
I do not know if the right term is a paradox but you seem to be saying that customers in a trillion dollar industry are bitching and moaning that they are paying a” $4 billion tax”.
Exactly right! I think it is irrational but it is not the value that EDA delivers. I am EDA’s strongest supporter when it comes to the output of the R&D teams in EDA. I would put those people up against any other segment in the world in terms of the ubiquity of the tools they make multiplied by the complexity of the problems they solve. No one solves a bigger universe of problems than EDA. The problem is this though, they want to be paid upfront regardless of whether the product is a success or failure. That is not the climate in the semiconductor world. It is not a question of fairness. That is a religious concept. It is a question of the marketplace and what semiconductor companies are willing or not willing to do. They are not willing to pay EDA top dollar upfront for a project that is super high risk and may never see the light of day.
What percentage of design starts never sees the light of day?
I would say that it is in the area that 90% of designs are never manufactured at all, yet alone with any volume. In our business about 50% of the chips we work on go to production which is huge and we work hard to pick the winners. On average it might be 15% go to production but I doubt it.
If I heard you right, EDA’s pricing model should be more like IP where there is some upfront payment, reduced compared to current pricing, but there is some royalty payments (pennies per chip).
Absolutely right! It is some version of that. If you think about what my business model does, I buy EDA tools like everybody else, work hard to negotiate the possible price I can, then I monetize that without which I could not have a company into participating in the semiconductor part of the business bit the EDA part. eSilicon draws its value, create its value, in a $250 billion semiconductor segment, whereas EDA tries to extract value from the $4 billion EDA segment. I would rather be sharing a $250 billion pie than a $4 billion pie. One way they could do that as you suggest is by having an upfront fee and going to a royalty basis like IP which would be a half-step. My personal view is that EDA companies need to be shipping silicon and participating on that. The simple fact is that there are probably 10 companies in the world that will own fabs in the next couple of years. It might be less already. Anybody can baby sit the supply chain. They are poised to do as good a job as anybody else but they elect not to do it because of some misguided motions of what the semiconductor model would do to their gross margins or their balance sheets. It does not have to be that way but they have not stopped to take a look. If you are thinking right now that I am arguing for them to compete with me, I am trying to extract myself from my company and talk about the industry at large and as someone who has spent is career here EDA could come up with a better business model than they have.
Soliciting free advice on behalf of the EDA industry, other than the model I described which you described as a half-step, what would you advise?
Besides the half-step, what else could they do?
Yes!
My view is that the large EDA companies should be delivering their value in silicon with the customer’s name on it. That’s what the customers want. That’s with the supply chain is set up to do. It is a way to share in the upside and the downside. The EDA tools have been relegated for one reason or another and we can go back into the history of EDA to a non-valued participant in the overall semiconductor industry. While it is not right, the way to transcend that is to really participate in the thing that the people who buy EDA tools really want which is silicon that works with their names on it. I an arguing that EDA companies should in fact be delivering silicon, not unlike what the fabless semiconductor companies are doing today.
Would you still say that if someone waved a magic wand and the global recession ended tomorrow?
This is a problem that is not due to but only exacerbated by the current economic condition. It is still a $4 billion industry with no growth potential. Absolutely! It has been flat for 10 years, in the best of times (I don’t want to sound too Dickenesque) and in the worst of times. It is only shrinking now. Cadence is struggling. Magma is struggling. Synopsys is temporarily enjoying the fruits of their downfall but it is an ebb and flow process going back and forth for a decade. They are not creating new markets but taking market share in the short term. But that market is shrinking. There are just fewer people to buy EDA tools, period. The recession exacerbates that but ironically it doesn’t exacerbate it to the same degree as for other industries because design continues. The big costs are masks, the tapeouts, and the productization. Design will continue. They don’t feel the same pressure as the rest of the world. But when this corrects and comes back, EDA is not going to come back. EDA will be worse off in two years that it is today, regardless of what the economy does.
Thank you.
More about the state of the EDA industry will appear soon in the upcoming fourth quarter and 2008 commentary on this website
The top articles over the last two weeks as determined by the number of readers were:
Mentor Graphics Appoints General Managers Mentor appointed Robert Hum as VP and GM of the Deep Submicron Division, Glenn Perry as GM of the Embedded Systems Division, and Guy Moshe as GM of the Design Creation business unit in the Design Creation Synthesis Division.
Robert Hum, who formerly served as vice president and general manager of Mentor’s Design Verification and Test Division, joined Mentor Graphics with the IKOS Systems acquisition in 2002. Glenn Perry has served as the general manager of the ESL-HDL Design business unit at Mentor Graphics since 2004. He joined Mentor in 1999 as the engineering director for system-level simulation tools. Guy Moshe has been with Mentor for four years and has held product line management responsibilities for the Vista product line, and the former Summit Design product lines.
Synopsys Posts Strong Financial Results for First Quarter Fiscal Year 2009; Earnings Up 13%, Revenue Up 7.7% On Feb. 18th Synopsys reported results for its first quarter ended January 31, 2009. For the quarter Synopsys reported revenue of $339.8 million, a 7.7 percent increase compared to $315.5 million for the first quarter of fiscal 2008. Net income for the quarter was $52.4 million, or $0.37 per share, compared to $46.4 million, or $0.31 per share, for the first quarter of fiscal 2008. The company expects revenue in the next quarter to be in the range of $332 million to $340 million.
SpringSoft Agrees to Acquire Certess SpringSoft, Inc. has signed a definitive agreement to acquire all the outstanding shares of Certess, Inc., creators of the
Certitude™ Functional Qualification solution. Pending customary shareholder and regulatory approvals, Certess will become a wholly owned subsidiary of SpringSoft USA, Inc. and its operations will be integrated with SpringSoft’s global development, sales, support and marketing functions. Certess employs 20 people primarily in France and the United States. SpringSoft will retain Certess’s entire R&D operation in France, which will report to Yu-Chin Hsu, Vice President of Logic Verification R&D, and will fold the Certess field sales and support personnel into its global channel. Certess CEO Michel Courtoy will stay with the company in a non-executive consulting role.
Magma Third Quarter Earnings Call Rescheduled to 1:30 p.m. PST Magma Design Automation Inc. (Nasdaq:LAVA) will conduct its third quarter earnings call at 1:30 p.m. PST on Feb. 26, 2009, 30 minutes earlier than previously scheduled, to avoid a conflict with another company's earnings call.
Jasper Design Automation Raises $7 Million in Series D Funding Jasper announced it has raised $7 million in Series D financing. The investment round was led by new investor, ZenShin Capital of Menlo Park. Joining the financing were existing investors: Accel Partners, Cambrian Ventures, Foundation Capital, InnovationsKapital, and Northzone Ventures. The funds will provide working capital to support Jasper’s self-sufficient operations and continued market and product expansion.
Tela Innovations Acquires Blaze DFM Tela Innovations, has acquired Blaze DFM, a supplier of technology to reduce power in advanced manufacturing process nodes. The acquisition brings Blaze DFM’s complete line of products and technologies, including Blaze MO™ power-optimization technology, into the Tela portfolio. Key engineering personnel will join the company to enable continuity of product development and support of customers. In 2008 Blaze announced an agreement with TSMC that launched the foundry’s PowerTrim™ Service. This exclusive service provides TSMC customers with a unique solution that blends Blaze DFM’s design technology with special tuned advanced semiconductor processes to improve power consumption.
Other EDA News
Synopsys CEO Aart De Geus to Speak at Morgan Stanley Technology Conference
ISQED 2009 Announces Multiple Interactive Tutorials
Azuro Launches Rubix™ Clock Concurrent Optimization Tool
OVM Extended to Efficiently Manage Coverage Metrics
Synopsys Enhances DesignWare DDR PHY IP with Service to Verify Signal Integrity
TI EDA Executive Mike Fazeli Joins Atrenta Team
Arena Solutions Announces Record Growth in New Bookings and Net Retention for the Fourth Quarter and Fiscal Year 2008
ISQED 2009 Announces Multiple Interactive Tutorials
AMD Selects Cadence Incisive Palladium Series to Verify Complex Graphics Design
QThink Design Services Adopts Magma's Titan and Talus to Implement Next-Generation Mixed Signal Designs
HP and Sun Microsystems Sign Multi-year Partnership Agreement for Solaris on HP ProLiant Servers
Open Text Helps to Reduce Infrastructure Costs and Improve Remote User Experience with Release of Exceed onDemand 7
MIPS Technologies Selects Berkeley Design Automation Analog FastSPICE™ Platform and AFS Nano™
SiSoft Wins DesignCon 2009 Best Paper Award for "A Simple Via Experiment"
Srikanth Chandrasekaran to Receive Accellera’s 2009 Technical Excellence Award at DVCon
Certess Announces the First C-Level Functional Qualification Tool
Synopsys, Powerchip and Nikon Collaborate on 42-nm Flash Memory Optimization
Altium Further Extends the Appeal and Ease of FPGA-Based Design
Tela Innovations Acquires Blaze DFM
20 Electronics Industry Leaders Collaborate to Accelerate Development and Adoption of Design for e-beam Technology
Srikanth Chandrasekaran to Receive Accellera's 2009 Technical Excellence Award at DVCon on Wednesday, February 25, 2009, Doubletree Hotel, San Jose, California
Magma's Latest Version of Talus Vortex Delivers Industry-Best Quality of Results for Advanced Designs (Magma)
Agilent Technologies Announces High-Frequency/High-Speed EDA Release for Integrated Circuit, Package and Board Co-Design
Teklatech’s FloorDirector™ Tool Compatible with Sigrity’s XcitePI Power Integrity Simulation Flow
SpringSoft Agrees to Acquire Certess
Tieto Joins Atrenta’s SpyLinks™ Partner Program
Mentor Graphics Appoints General Managers
Industry's First Low Power Verification Methodology Manual, Authored by ARM, Renesas Technology and Synopsys, is Now Available
Jasper Design Automation Introduces Design Activation Services To Promote IP and Design Reuse, Driving Higher Customer ROI
Zocalo Tech, Inc. Introduces First EDA Tool Dedicated to Assertion Library Productivity
Simulation Helps Keep One of World’s Top Data Centers Cool (Mentor Graphics)
Epson’s Semiconductor Division Extends Deployment of SpringSoft Automated Debug System
Accellera Invites EDA Community to Attend Its Luncheon, OVL Survey and Technical Excellence Award Presentations at DVCon
Mark Your Calendars: DVCon 2009 to Deliver Rich Technical Program
Magma Enhances SiliconSmart With New Functional Recognition Capabilities, Speeding Modeling of Complex Standard Cells and I/Os
Synopsys Posts Strong Financial Results for First Quarter Fiscal Year 2009
Mentor Graphics’ Walden Rhines and Intel’s Paolo Gargini Receive Prestigious IEC Fellow Awards at DesignCon 2009
HP Reports First Quarter 2009 Results
LSI Corporation Selects Synopsys as Its Primary EDA Partner
Jasper Design Automation Raises $7 Million in Series D Funding
Independent BDTI Benchmarks Recognize CEVA-TeakLite-III as Most Area Efficient and Energy Efficient of all Processors in Its Class
ARTEMISIA Association and DATE 09 Conference Join Forces
Other Embedded, IP & SoC News
Toshiba Adds 40V, 60V and 80V MOSFETs for Isolated DC-DC Bus Converters Using Sixth Generation High Speed Process for High Power Efficiency
STMicroelectronics Increases Power Output of Portable Stereo Amplifiers Featuring 3D Audio Capabilities
Atmel Introduces the First IEEE P802.15.4c Compliant RF Transceiver Tailored to the Chinese Wireless Market
SMSC Introduces Industry’s Smallest, Full-Featured 7-Port Hi-Speed USB 2.0 Hub Controller
AMD Demos Upcoming Six-core “Istanbul” Server Processor
IAR Systems: Faster ARM Cortex-M3 Processor Debugging with New Release of IAR Embedded Workbench
Economic Reality Will Drive a 22% Decline in Global Semiconductor Sales This Year, IDC Says
Lime Microsystems selects Jazz Semiconductor’s 0.18-micron SiGe process for its Configurable Multi-band, Multi-standard Transceiver Targeting WCDMA, CDMA, LTE and WiMAX Femtocells
MOSAID Expands Into New Markets with Acquisition of 300 Communications Patents
Maxim and Universal Electronics Purchase Zilog Universal Remote Control and Secure Transaction Businesses
Innovative Logic announces USB3.0 Device Controller IP
ARC International plc Announces Unaudited Preliminary Results For the Year Ended December 31, 2008
NextIO Adopts Denali's Verification IP for New PCI Express Expansion and I/O Virtualization Module for Blade Systems
Rambus to Host Conference Call to Discuss Recent Legal Developments
ON Semiconductor Launches 6-Watt LED Driver with Integrated DC-DC Boost Converter for Larger LCD Panel Backlighting
STMicroelectronics Promotes Green Power for Electronics
TSMC and Tela Innovations Announce Strategic Partnership to Enhance Design and Process Co-Optimization
In Another Favorable Preliminary Ruling, U.S. Patent & Trademark Office Rejects All Claims of Third Patent Asserted Against Aruba Networks by Motorola
Micron Technology Responds to Continued Decreases in Demand
Court Grants Rambus Supplemental Damages in Hynix Case and Orders Negotiation of Compulsory License
SRS Labs Reports Fourth Quarter and Year End 2008 Results
Sundance SMT712 Module Optimized for High Bandwidth Applications Enabled by PXI Express. Expands SundancePXI Express Multiprocessor Solutions
Accordance Launches 1U Height M200 eSATA/SATA RAID Controller with Two 2.5 Inch Laptop Drives for industrial and embedded applications
ARM Showcases Innovation in Mobile Technology at 2009 GSMA Mobile World Congress
Strength of the ARM Ecosystem Demonstrated at MWC with More Than 60 Partners Showing ARM Technology
Tower Semiconductor and Triune Systems to Collaborate on Power Management Platform
Tata Elxsi announces multicore DSP-based WiMAX base station and carrier class CPE for public safety and defence applications.
United States Supreme Court Denies FTC Request to Review Rambus Matter
NMI: Conference Shows How to Manage CMOS Variability
ChipMOS TERMINATES SERVICE AGREEMENT WITH A LEADING NOR FLASH MAKER IN THE US
Lattice Accelerates Development Time With New Reference Designs Optimized for Popular MachXO PLD Family
Leadis Technology Opens LED "In-Situ" Temperature Compensation Engine for Licensing to Third Parties
Lattice Announces ispLEVER 7.2 Service Pack 1 FPGA Design Tool Suite
Lattice Launches Industry's Lowest Power, Highest Value FPGA Devices
Lattice Announces New Mixed-Signal Design Software Tool Suite
Lattice Announces Ultra-Low Phase Noise, Zero-Delay Buffer Clock Family
ARM Launches Its Smallest, Lowest Power, Most Energy Efficient Processor
North American Semiconductor Equipment Industry Posts January 2009 Book-to-Bill Ratio of 0.48