Introduction
I had a chance to interview at length Keith Mueller, currently the VP of Worldwide Sales and Marketing at Apache Design Solutions. Keith has had a very successful track record as an entrepreneur in the industry. His partner is Andrew Yang, the company CEO. Keith will share below his opinions based on his past successes about how to create a successful company as well as their current approach at Apache.
Mr Mueller
We are ~4.5 years old at this point. My last startup by the way was SPC, Silicon Perspective Corporation. This thing is on a very similar track. It has been kind of interesting. We both had the same amount of money, around $5 million. This is pretty small compared to Magma and Monterey, each of whom took around $115 million to get started. Sequence is probably in the range of $80 to $90 million. I don't know the exact numbers. We are kind of on the extreme low end. The other company that Andrew and I were involved with and where we first met each other was Anagram. Anagram was a circuit simulator. It was kind of the first generation HSPICE. In fact we were competing with EPIC at the time with their TimeMill. The product was called ADM. We had a really tech sounding terms for what the letters stood for. I don't remember it now. Andrew was actually the founder of that company. He was a professor at the University of Washington at the time. He got a couple of his graduate students, locked them in an apartment and fed them food and water under the door until they got the program done. Then we started the company, Soliday. That one took $100K to get started. We sold it to Avant! for $74 million after about a year and a half. You can see the central philosophy of the company: Let's minimize the expenses. Let's not get a lot of marketing hype. Let's not get a beautiful lobby. Let's not build volcanoes like Magma did. Let's focus on customers and customers' success. Then there's the other extreme that kind of hypes themselves with a lot of money and marketing dollars and goes that route. There seems to be two diametrically opposed approaches to doing a startup. A software company shouldn't take that much cash. There are no NREs, there are no hardware expenses, there's no nothing.
Did Andrew do the same thing with this company, i.e. lockup a bunch of graduate students? Where did the technology come from?
This one he did a little bit more formally. He actually grew up. When he got acquired, he left the University and joined Avant!. He ran the simulation and the StarRC team for a couple of years under Gerry Hsu. He actually retired at that point for about 4 years. When he was “retired”, he did a lot of investing in EDA companies. He was the lead investor in CADMOS. He invested in Sapphire which became part of Sequence. Until the beginning of this year when Sequence had to reorganize and refinance the entire company, he was a major stockholder in Sequence. Mohave was one of his recent investments. He was the lead investor. He sold that one to Magma about a year and a half ago. He has been doing a lot of that.
The technical founders of Apache are Shen Lin and Norman Chang. These guys came from HP Labs and Shen worked previously at IBM. They weren't EDA veterans. The technical guys were published. They have written a book on “Interconnect Analysis and Synthesis”, so they are well renowned in their field. The common link was that they were inside the labs at HP and at IBM. This is their first venture company. The good news is that we have these very sharp technical guys and we have Andrew and me, who are kind of serial entrepreneur types. This is our fifth EDA startup. It goes all the way back to Silicon Compiler which was acquired by Mentor Graphics, onto QuickTurn which went public, onto Anagram which got acquired by Avant!, on to SPC which got acquired by Cadence. Now this one! We have some experience as well as some new highly energetic fresh blood working on this new area. I didn't know Andrew before Anagram. I knew the president, Edmund Chang from Silicon Compliers. That's how I got into Anagram. I met Andrew there. In my experience sometimes a CEO can be very good technically and not so good business wise. On the other extreme they can be very good businesslike but not so good technically. Andrew is one of the few CEOs that I have met that is actually very strong on both sides. This is evidenced by his record both being a professor and obviously knowing the technical side and also being able to fund and envision what's coming next. When you are doing a startup, you want to do something unique. You want to be ahead of the market. You don't want to compete just on capacity and speed because that is very fleeting and in difficult economies it doesn't even get you orders. You have to view something that is coming and maybe isn't quite there but you don't want to be too far ahead, where you can't survive long enough for the market to realize you are right. I think that that one of his real strengths is being able to envision what's coming, what the next issues are and be ready for them when the issue comes to the marketplace. I think that's what had happened with Apache.
Basically we are focusing on noise and the noise comes from different areas. Our first real endeavor was the power supply but it also encompassed the package. We take package models either RLC or S models and we include the effects of those. One of our products looks at the chip including the power grid, checks the power grid and IOs out through the package onto the board. We can simulate that whole path. As these busses get wider and the currents get dramatically faster and the edge rate go up, on chip inductance as well as packaging inductance becomes significant. We have been extracting on-chip inductance for several years. Only people doing high frequency, 1 GigaHz plus type designs, need to worry about that at this point. But there are more and more designs getting into that space. Looking from the border of the package including IOs out is an area where they have been different DDR interfaces and some graphics interfaces that are extremely fast. These can cause issues when those IO switch at the same time.
As you go down to 65 nm and below there are things like on-chip variation in this space. We are not playing in all of them at the current time. We are taking it one by one. We now also have tools in place to handle the leakage issue and some of the advanced techniques that TI and Qualcomm and some of these wireless guys are using to reduce leakage currents by headers or switches to completely cut off different parts of the circuit and disconnect even the leakage current. We have the ability to analyze that effect when you turn it back on, the transient effects turning on different parts of the circuit at different times. We are focused on the leakage area as well. Both from an accuracy standpoint you have to accurately predict the leakage current and then be able to analyze the advanced techniques that customers are using to really control leakages switches become more and more critical.
Signal integrity is an area we just got into. At DAC this year we announced a product called PSI Sidewinder where P stands for power and SI is for Signal Integrity. This is the first product that concurrently analyzes the effects of signal integrity and power integrity. From the chip's standpoint it really doesn't know if this noise is coming from power or from signal. It doesn't really care. It just knows that the timing and some of the other aspects of the chip have been affected by the noise. This is a tool that helps analyze them together.
This is what we have been doing in the past. Early on everybody was using statics. Statics was pretty gross. If you look at the published material, Simplex started in the 1996 timeframe. It's been around going on 10 years now. It was a technique that at least lets you see grossly, just looking at resistive effects of the grid and average currents, whether you have any major problems with the grid. It also took so long. If you went through verification and found a problem late in the cycle and you had to fix it, it had a major impact on time to market. You basically had to re-floorplan and redo some of the chip. Since Simplex was a verification solution, you ran it at the end before you went to the fab. People didn't want to find a problem, so they tended to over design the hell out of the grid to make sure that when they went to verification, there was no issue. The problem with that is that it wastes a lot of resources. Whenever you use metal for power and ground, it eliminates those tracks from routing which means you have a more difficult route to design. It obviously wastes area which means if you are in a very competitive consumer market, you will have difficulty. It can also impact performance. There are a lot of tradeoffs but nobody had a better solution for doing it and it lived for a long time.
In the last few years you would not believe the number of customers that have come to us with chips that have passed the latest flow which at that point was still static. The chip goes through the final verification step, it gets passed on static and it comes back. Either it doesn't work at all or it doesn't work in scan mode which seems like an easy problem but it is really a worse case of simultaneous switching type of problem or it has no yield and they can't figure out why. It turns out that it is because of the inaccurate analysis inherent in the static approach where you are looking at average currents and resistance of the network only. You can not see some of the effects that are actually happening, especially in these more advanced processes. That's what Andrew saw ahead of time. When we got there, people started coming to us. We were able to predict accurately what was going to happen, i.e. that the issue would become a major point of concern for the customer. That's kind of where we are today.
The next kind of solution to arise was the iterative solution. We also played in this area. We focused on doing power integrity, looking at dynamic effects, the simultaneous switching effects of the power. If you have multiple drivers on the bus on the chip, what is the impact of those multiple busses changing at the same time on the voltage drop? We call it DVD, dynamic voltage drop. How does that impact the timing, since the drive to some of these gates have changed? How do you analyze and determine exactly what the voltage looks like at that point? What the wavefront is? Not just the voltage but what the wavefront looks like. How do you highlight what the waveforms effects are on the timing and the delay of that gate? That's what we have been focused on. Other people have focused on signal integrity. Everybody been kind of taking and analyzing the pieces separately. Now we are moving to this Sidewinder product, which analyzes the concurrent impact on timing and operation of the chip. The chip doesn't really care which noise it is. It just knows it has noise from multiple sources and what's the impact on the timing and operation of the chip based upon that noise. We are moving more and more towards this concurrent approach. The difficulty is the complexity goes up. You need to have more accuracy in these approaches. That changes the scope of the job. If you look at our particular market in dynamics, some of the things that happened was that the big guys, especially Cadence and Synopsys that were basically splitting the market between AstroRail and VoltageStorm for static analysis, had underestimated the task of taking it from static and actually look at the dynamic characteristics.
Cadence and Synopsys were promising customers literally for 2 years with a 6 month rolling forecast that this capability would be there. They promised that they would be there and it has yet to happen with a viable product which is why we pretty much own this particular market. The customers view this area as very critical and the big guys haven't been able to perform because of its complexity. They treat statics as Ohm's law. It is V=IR, very simple; big I for average current, R for resistance only. What we are solving is a dynamic waveform that looks at the instantaneous current effects. Since it is instantaneous, it has edges and transitions. The di/dt affects the inductance on the chip or on the package. Also decap is built into the chip intrinsically, just by the fact that you built the chip there is a certain decap that is included. If you characterize the chip, you can get what the decap is for each cell, for the power grid and everything else. You include those types of effects as well. It's just a tremendously different complexity level. Out of the other 5 startups I have done this is the most complex challenge that we have ever undertaken. I think the other guys really underestimated the problem.
Some of the keys to analysis is looking at each and every level of characterization. You need to handle full chip. As you know, for some of the designs for graphics vendors (e.g. ATI) guys, and for some of designs for communication networks, chips get immense; up to 50M to 60M gates, if not more in some cases. It's just a tremendous complexity. There are full chip issues. One area of the chip can affect another part of the chip. So you can't really separate it looking at different sections one at a time. It really needs to be done on a full chip basis and it needs to be done accurately. The way people have been done full chip in the past is that you extract and try to simplify. We had to do the same thing to some extent but we are careful to then take a look at the lower level and characterize those extremely carefully at the transistor level so that when we extract things off, we have a very accurate model of what the switching current looks like. We have the exact waveform for each of the instances, for each of the gates based upon the load and the supply that they happen to see. That's how we try to maintain transistor level accuracy, even though we are looking at cell based capacity. The other problem that people have is on a full chip basis, they don't know exactly which vectors are going to create the worse case dynamic voltage drop and therefore impact the timing the most. It's too complex a problem for an engineer to work through even a reasonably sized block much less a full chip to really establish that this is the worse case vector set and is guaranteed to cover all the conditions.
We had to develop an approach that first looks at the effects and creates scenarios that are statistically valid that look at which instances based upon the timing information we have can even switch together at the same time and carry that forward to try to get a realistic worse case expectation without the ability to have detailed vectors from the customer. If they have vectors, we can run them. Some times this is a good way to correlate things. But in general, it does not give you a true worse case picture. We cover that area as well.
We have also been focused on sign-off. We have actually become a sign-off requirement at a number of different customers now for dynamic. Different customers create different criteria for doing this. It is interesting to watch. Some are timing based. Ultimately they do not care what the DVD is, if the timing of the chip works and it functions correctly. Some people put a limit on it. They use a 5% to 10% limit on static. They have a much higher limit by necessity on dynamic drop, maybe 3X larger or more than static drop. We have learned a lot over time. That's the thing that I think keeps us ahead. The experience you get from doing 150 to 250 tapeouts, working with real customers on real projects, gives you a lead that even when other guys come out with a solution, it is really hard for them to catch up with that experience. It has been interesting to watch.
When you do find problems, how do you fix them, repair them? You have talked to Sequence about the CoolCheck product that they came out with. We have that technology in our products for over a year and customers are using it. Not that it isn't good, it's just really old news. This whole “fix and repair thing” is what we have already been doing with customers.
We have been shipping the dynamic version of RedHawk for over two years now. It came out in August 2003. The first tapeout was in that quarter. As a result of that we have been cash flow positive which is a key metric for a startup. If you are not cash flow positive, then you have to keep looking for investors to invest more money and further dilute the employees and dilute the company. That makes a tremendous difference. That's why we have been able to servive on $5 million and get up to roughly 70 people at this point. I don't think there is any other startup out there that has that track record.
How much revenue does Apache generate?
We don't specifically say. We are privately held. In the next day or two we are announcing that this is our first quarter of profitability. So if we are profitable with 70 people, then that will give you a reasonable estimate. It's been fun. One of the things that really helped us was that back in 2004 we were the only vendor out of Cadence, Synopsys and Magma that was in TSMC Reference Flow 5.0 for dynamic analysis, for I/O SSO (Simultaneous-Switching Output) analysis. The reason we got there so quickly is because we actually had one of their customers that had a chip that had a failure. They ended up using our product internally to identify the failure. Through that process we got correlation to the silicon completed. They were able to get the design fixed. We became the only vendor in their reference flow. This was back in 2004. We are still in that reference flow. Politically they have added Cadence and Synopsys to it.
Broadcom is gong to announce this week that we that we won the business with 5 other vendors competing. We handily won that. Here again this was based upon our experience, the maturity of the product, the ease of use, those sorts of things. We were also lucky enough to get the Developer of Year award. We were nominated for Innovation of the Year. I think we came in second to AMD Opteron. The AMD 64 bit processor team beat us out. We did get the Best Development Team of the Year award from ED Times for the RedHawk development guide. That was a good boost as well.
The real thing was having that TSMC signoff. We were then able to get some deals that didn't require a benchmark because their vendor had authorized us and said that we were certified for tapeout. We were able to get some deals without doing a benchmark which is a wonderful thing when you are in EDA; to avoid that exercise to prove that you can do what you say you can do. At this point we are at 11 consecutive record quarters. Every quarter has been monotonically up. There are very few startups even SPC with the success that we had there that can say that. At SPC we took in $5 million and sold it for $430 million to Cadence. At the end of the day after all earnouts it was about $435 million. Even with that one we had some up quarters and then we would go down. The trend was always in the right direction. But it was much more up and then down, up and then down than this one which has been monotonic which is pretty exciting and now reaching profitability for the first time. We are 100% time based licensing (TBL). That's why we can be cash flow positive. When we sell a license for 1 or 3 years, we get all the money upfront but we recognize the revenue conservatively over the period of time the customer has the license. Let's say that we get $1.2 million this year, we would recognize $100K each month as revenue even though we get the $1.2 million upfront. That's why we can be cash flow positive. We can cover our expenses using customers' money. We get that net 30 days. We take the revenue that's really counted against expenses to determine whether we are profitable or not. We do that conservatively over the period. The good news is that the customer base repeats. We have never lost a renewal yet. We expect that business again in the future and build upon it. This is a very consistent, predictable revenue flow once you get it going. That's why all the big guys in the past couple of years have switched to being time based. When you look at when they do their reports, they report what percentage is time based versus perpetual.
Are your sales direct, indirect, a mixture?
It's another unique thing I think from a startup standpoint. We did it before at SCP and we are doing it again here. We are direct everywhere around the world. We started with a distributor in Japan with Apache here. We did the same thing as well with SPC but eventually we went direct. We did that quickly here. Now we are direct in every single country. We found with distributors that it is such a complex sale, such a complex problem that trying to get a distributor that has all these different products in his bag to really give you and the customer enough focus and get good enough to really support the customer just doesn't work. We have gone direct in Korea, Taiwan, India, Japan and of course the foreign country of Texas.
You have stressed your approach of taking very little money. How do you differently in order to attract customers, build up a reputation, …?
It's really the same thing we did at SPC. If you look back at their history we were a very quiet company. The original name of the company was Reload Design Automation. We didn't want anybody to know what we were doing. We did everything to avoid being high profile. We simply focused on our new customers with real problems that our unique technology could benefit and then worked closely with them to make them successful and let that success breed additional successes. Use those as references and go on and build some more customers. If you look at SPC, nobody knew us from Adam for a long time. Then Cooley did his famous or infamous (depending on your perspective) tapeout survey of all these physical prototyping tools; Physical Complier at the time, Monterey also had a solution they were pushing. If you look at that survey, we came out number two to Physical Compiler. Everybody was just shocked because no one had ever heard of us except the customers we had been working with. Yet here we were number 2, above everybody including Monterey who was making hype about having customers. If you notice, Cooley really embarrassed them. He said, “Let me do a recount; number of tapeouts zero.” It was pretty funny at the time, although I am sure it wasn't to Monterey. But he wanted to get rid of all the hype. So if you are hyping your product, if you are doing a bunch of press overstating what the real situation was with customers, it was Cooley's goal to uncover all of that hype. Only if you had real customers that did a real tapeout would he count it as a tapeout. He did a good job of doing that. That put SPC on the map because we had been quiet, nobody knew who we were. Then when he actually did the survey, we had all kinds of customer success. It's exactly the same approach we did here. We weren't hyping ourselves. We weren't over broadcasting what our customers were doing. We tried to do the same thing here. Tried to stay straight, working with customers on unique problems, coming up with solutions, and making it a success.
Editor's note: A Cooley survey in late 2000 reported Synopsys with 65 tapeouts and SPC with 43 tapeouts.
I understand what you didn't do and I understand the risk one might have if one over hypes his product. But how do you penetrate early prospects with a stealth strategy, benchmarking, superior salesmanship, ..?
I think this is one case where your experience and track record can actually help tremendously and I am not trying to blow my own horn here. You've asked a good question. I will give you a little example. I had sold Anagram into AMD. They liked the product and we made that successful. I didn't really know the team at the time, so it was the usual path to get into AMD the first time with Anagram. We went through the benchmark and ended up wining the business. We got there with a unique and good product. We supported them and made them happy. That got me a number of people that appreciated the fact that we got them out of hot water on one project. They liked the technology that we brought them in the first place. Then when I went to SPC, I was able to go back to the same guy, John Vitello who was the CAD manager for a long time. I was able to go back to him. I let him know what we were doing at SPC. He said that he was in trouble. They were working on a design which was right now in the middle of tapeout and he couldn't really afford to talk to talk to me then but maybe in a month. I called him back in a month and he was still in trouble. I said that I know this is an area where I can help you. I know the problem you are suffering and I think that this is exactly what we are trying to address. Just give me an hour to come in and show you what we do. So the fact that John had brought in technology that had helped them before, gave us enough credibility to get back in there, gave us a chance to get their design team together, show them what we could do. Then we started a quick benchmark. They had this design that they had been working on and couldn't quite get timing closure. We started doing the same design in parallel without distracting the team. We put our VP of Engineering, who was also my super secret guru, onsite at AMD. He got up to the same stage where they were, duplicated everything they had done in 3 days. They had been working on it for a long time. Then we were able to show them how to solve the problem quickly. They liked what we did and they bought 2 licenses. We didn't have to negotiate the price. We put these onsite, supported them and made them successful. We leveraged that into other sales. When I went to AMD again with Apache, it helped us to get access because of past experiences. If you were true with somebody before with a real product that wasn't hyped, that really worked, and that made them successful, it helps to get in the next time.
If you have 90% market share and 6 out of the top 10 fabless companies and 35 customers worldwide, where will the revenue growth come form (new customers, existing customers, ..)?
It's really a combination of both. You've got to remember that the nice thing about monotonic revenue and the fact that it is all time based license is that as long as you are keeping the customers happy and you get renewals - so far we have 100% renewal rate - that means that you are only building up from that level. So if I get one new customer each quarter, that would give me a monotonic increase every year. I still get the old business from previously booked orders. If I get a three year agreement, I only count one year in my bookings. There are no games. You don't try to celebrate revenues like some of the games the big guys played and got into trouble with. Everything is ratable. If I want to grow next quarter and I add just open customer, I automatically have growth. By the way that growth pattern wouldn't support where we are with so many people and being profitable. We have been growing an average of 20% quarter to quarter over the last couple of years. So growth per quarter is on average pretty high as well.
Small companies often have substantial growth quarter-to-quarter and certainly year-over-year largely because the baseline is so low. If I guess that you are now around $10 million revenue, how do you grow to $100 million, if you already have 90% market share?
First some of the growth in fact a lot of the growth is coming from the top 3 fabless companies, multiyear and multimillion dollar deals. Some of the other guys aren't at that level yet. There is a lot of growth within the existing customer base to expand usage. Some of them are more on the 130 nm going down. Some are more aggressive. Others like ATI and Qualcomm are already doing 65 nm. It really depends upon where they are but they are all moving in the right direction to dramatically increase in our existing customer base. We have the top tier companies. Even in the firms with whom we have multiyear deals, I expect growth.
The next thing is new customers. In fact if you look at the Bell curve that shows the center of the technology for where most of the design starts are today, my feeling is that the center of the peak is in the 130 nm range but it is certainly moving down. There are customers still doing 150 and 180. There are still a lot moving to 130 and 90. Looking at dynamics issues becomes mandatory. They need to get that capability to do those types of design, whereas they could get away with grosser approximations when the power supply is 1 volt for a 1.8 micron design. If you have a 1.8 volt power supply, you have a lot more noise margin to work with than with a 90 nm process at 1 volt. The issues become more and more significant. The accuracy requirement of noise, more detail about what's going to happen become more critical at 1 volt. Everything is moving in the right direction for us.
The third thing is growth in the product line itself. We are not just sitting still with just one product waiting for everybody to catch us. The product itself keeps on moving. We don't stand still for a minute. We don't want to wait until somebody catches up. If they finally do what we did two years ago, we want to have enough new capability to differentiate us so that they can't just bundle it in with other Cadence or Synopsys products. We have to stay unique in our offering. We use Redhawk as a platform and go into the Sidewinder type of product where we are working on things in thermal and other areas that will all tie together and give us broader capabilities. That adds new products which mean more revenue to grow these accounts and to increase overall size.
Even though we haven't much cash to do acquisitions we have already done what I would consider very strategic acquisitions in our life. One was before I got here three and a half years ago. It was the company that brought us NSPICE. NSPICE was not originally an Apache product. We acquired a company. It turns out the guy had been an employee at Anagram. This is so small an industry that you see the same people over and over again. We acquired that guy's company. It was a small company, only two people. They had a few customers. The reason we did it was that having that capability for that technology not only helped us with the characterization of the cells that we have to do with dynamics but it also helped verify the accuracy that we are so focused on for dynamic as well. It is unique but a true SPICE simulation just like HSPICE. We could literally go with NSPICE, it's faster and better. But there's a religious fight that we choose not to do. It is not worth it. The market is established, the price is already down. It is a religious thing trying to replace HSPICE but technically it could. We use that instead more strategically within the company to do the things we want to do in unique areas that other people don't play in. We acquired another small company that got us into the signal integrity space. We were primarily focused on power integrity and now we have the SI piece as well. Again a smaller company with some key customers. The real thing is the key technology that we leveraged in. We did this with stock. Everything thing we have done so far has been non-dilutive. The benefits that we get far exceed the percentage of the company we give up. That's the way we have done it so far.
The third point is one I can not underestimate. The maturity you get from actually working with these customers on real projects for so long a time. That's the biggest obstacle. Everybody else including Synopsys and other firms with a lot more resource than we have, can dump people on the product and they have I am sure. But they haven't been able to deliver because it is such a complex problem. But they could try and I am sure they have tried to accelerate development but once you get it out, the growth of the product from that point on is what you can not really compress. You finally get the projects but you still have to get the experience; with every project you do, you learn something new. It's that experience that you really can't replace and compete with.
What is the pricing of some of your products?
The list price for RedHawk starts at $180K per year with dynamics. Sidewinder is $150K/year. We created low end versions for some people that wanted to replace HSPICE in the range of $15K/year going up to $165K/year.
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Apache Achieves Record Third Quarter and Profitability; Customers Sign Multi-year, Multi-million Dollar Commitments Apache Design Solutions, the technology leader in physical power integrity solutions for system-on-chip (SoC) designs, today announced that the company has achieved its eleventh record-breaking quarter. Following eight consecutive quarters of being cash flow positive, the company achieved first-time profitability based on ratable revenue recognition of time-based licenses. See this weeks Editorial
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Synopsys to Highlight Liberty and Composite Current Source at 16th EDA Interoperability Developers' Forum
Sun Microsystems Reports Results for First Quarter Fiscal Year 2006
Electronics Workbench Announces Multisim 9 for Circuit Design and Simulation
Statistical Static Timing Analysis: How simple can we get? - Technical Paper from DAC 2005
Genesis Microchip Adopts Synopsys' DFT MAX Adaptive Scan
Formal Verification Is It Real Enough? - Technical Paper from DAC 2005
Cadence Chief Financial Officer Bill Porter to Present at the Morgan Stanley Software, Services, Internet & Networking Conference
Mentor Graphics Expands DFM Strategy with YieldAssist Diagnostics Tool for Yield Improvement
Exar Triples Verification Productivity Using Synopsys' VCS Solution With SystemVerilog Testbench Automation
Cadence Commences Trading under New Symbol 'CDNS'; Switch to Solely List on NASDAQ Complete
QuickLogic Lowest-Power FPGAs Supported by Precision Synthesis From Mentor Graphics
Faraday Technology Corporation Certifies EverCAD's ADiT-VPI as Co-Simulation Solution for Mixed-Signal Design
AWR Announces WiMAX Broadband Fixed-Wireless Design Capability for VSS Solution Originally Developed for TriQuint Semiconductor Provides Industry with an Important New Technology
Other IP & SoC News
AMI Semiconductor and MagnaChip Semiconductor Develop Specialized 0.18-Micron Process Technology; Relationship to Extend Support for Next Generation Medical Technologies
ISSI Announces Fourth Quarter and Fiscal Year 2005 Results
2005 FSA Suppliers Expo Taiwan & Semiconductor Leaders Forum Provides Industry with Enlightening Speeches and Technology Updates
SIA Applauds Agreement on Tariffs; Duties Eliminated on Multi-Chip Package Semiconductors
Infineon and Kineto Wireless Successfully Demonstrate World's First Internet Protocol Multimedia Subsystem Services Running Over Unlicensed Mobile Access Technology
Chipworks launches transistor characterization services
InterDigital Announces Third Quarter 2005 Financial Results; New Patent License Agreements Drive Strong Results
Chipidea Acquires TransDimension's USB IP Core Assets
Virage Logic to Showcase Silicon Aware IP(TM) for Increased Manufacturability and Optimized Yield at ITC
Tvia's LCD-TV Reference Design and TrueView(TM) 5600 Digital Display Processor Now Shipping in MiTAC LCD-TV's Worldwide
Atmel Achieves Higher Resolutions With Its 2.5M Pixel CMOS Industrial Camera
Actel Delivers Secure, Comprehensive Design Flow for Complex FPGA Development Using ARM7 Family Processor
Electronic Design Survey Shows 73 Percent of mainland China and Taiwan Engineers Design Asics Using 0.18-Micron Technology - up 21 Percentage Points From 2004
Tripath to Appeal Staff Determination Letter from NASDAQ
Teridian Semiconductor Introduces the World's Smallest Fast Ethernet PHY; Reduces Board Space by 70%, Targeted at Consumer Audio-Video Products
Pericom Semiconductor Announces Resignation of CFO
Altera Extends PCI Express Leadership With x8 Solution for Stratix II GX FPGAs
Analog Devices Introduces Multi-Channel Data Converters for Industrial and Automated Test Equipment Applications
Cypress Expands Industry's Most Popular Family of USB Microcontrollers With Next Generation Full-Speed and Low-Speed Flash-Based Offerings
Silicon Laboratories Deploys CEVA-Teak DSP Core in Industry's Most Highly-Integrated Single-Chip Phone for GSM/GPRS Handsets
Actel Holds First Annual FPGA Space Forum
Actel Increases MIL-STD-1553 Reliability With New Version of CORE1553BRT IP Core
Atmel Launches DVD-SoC Industry's Most Integrated and Powerful DVD-Single Chip
Sirenza Microdevices Announces Latest Addition to New Family of High Performance Broadband Amplifier ICs
Tower Semiconductor Begins Production of Biomorphic's 2.0 and 1.3-Megapixel CMOS Image Sensors for Cell Phones; Tower Technologies Result in Superior Sensor Capabilities for Camera-Enabled Devices
Silicon Image Extends Industry Leadership With HDMI Digital IP and Companion Sil9002 PHY Chip
Motorola Reaches Settlement in Zafirovski Lawsuit
ON Semiconductor Introduces Industry's First Floating, Regulated Charge Pump to Replace Isolated Power Supplies
Fairchild Semiconductor's 30V Synchronous Buck Chip Set Optimizes Efficiency and Space in IMVP4/6 Vcore Designs
STMicroelectronics Launches Second Generation AVC and VC-1 Decoder Enabling the Secure Digital Home to Become a Reality
Analog Devices' 3-Axis MEMS Accelerometer Available Now; Sets Ultra-Low Power Consumption Benchmark
National Semiconductor Introduces Industry's Lowest Phase Noise Single-Chip PLL + VCO
Global Semiconductor Sales up 5.2 Percent in September; SIA Says Consumer Demand Drove Strong Growth
Rio Design Automation Sets Sights on Emerging Package-Aware Chip Design Software Market; Startup Brings Together Experienced Team to Solve Challenge, Raises $5.25 Million from Cadence, Magma, Angel Investors
Freescale Unveils World's First 3G Single Core Modem for Mobile Phones
IVI Communications, Inc. Subsidiary is Featured by Motorola in an Industry-Wide White Paper