The news may be too late for some, but the evidence indicates that if you're an IC vendor and you haven't invested in design excellence, your long term prospects for success are compromised. This from Dr. Handel Jones, CEO of International Business Strategies Inc., who recently reported out on a 12-year study of the industry. Jones detailed his findings on a webcast broadcast November 22nd sponsored by Agere Systems and moderated by CMP's Ron Wilson.
His conclusion - companies with a commitment to design excellence have prevailed over those that restrict their emphasis to manufacturing capabilities. Jones backs up his assertions with hard-won evidence. He started formally tracking the industry in 1990 by asking customers to rank their IC vendors on a scale from 1 to 10 based on design capabilities, evaluating vendor effectiveness in meeting the customers' design requirements. Jones said he bypassed asking the IC vendors themselves, "They always say they're above average."
Through 1995, the emphasis of his study was on ASICs, however ASSPs have been a big part of the mix in recent years as well. Over this extended period, Jones has uncovered good correlation between customer satisfaction and IC vendors who display a long-term commitment to leadership design capabilities.
As the move to smaller geometries - .13 micron and below - drives the cost of product development into the $10 million to $20 million range, Jones said it's obvious that IC vendors can no longer overlook design excellence: using the best design tools, training their engineers to use those tools effectively, having access to top-quality, certified intellectual property (IP) cores, and attending to the multitude of factors that arise in today's complex designs, particularly those factors associated with co-design where software is inserted into the IC midst the hardware design phase and not later during the implementation phase. Jones added that the skyrocketing costs associated with all of this design excellence represents a significant barrier for smaller companies attempting to climb into the ring, and that established IC vendors will need to achieve higher levels of returns on their product offerings to recover the costs of attending to it all.
Jones pointed out that the entry fees for manufacturing capability - the costs associated with bringing a wafer fab on-line - run in the $2-$3 billion range, but the payback on that investment threatens to be increasingly limited without effective design capabilities. He said, those companies sporting strong design capabilities along with manufacturing, have a much higher market valuation than those who limit their strength to manufacturing alone.
His advice may come too late for some players, but it comes none too soon for the financial community who look to maximize return on their investments by going with the most promising IC vendors. Per Jones: "If you look at how committed a company is to implementing design capabilities, how effective they are in supporting customer needs, you can see correlation in terms of market position and market valuations." Point well taken.
Industry News
Synchronicity, Inc. announced the immediate availability of the Synchronicity Publisher Suite version 2.0. (Editor's note: This news was released prematurely in last week's newsletter. It is correctly included in this week's newsletter.) The new product has architectural enhancements to improve performance and scalability for very large, enterprise-wide deployments. Publisher Suite bundles the IP Gear Catalog and IP Gear Helpdesk, and provides design reuse and IP management and distribution in the electronics industry. Publisher Suite has been ported to the Oracle 9i database and can now also run on the PostgreSQL open source database.
Large semiconductor companies typically host reusable designs across several servers. Users may register those designs with the Publisher Suite 2.0 to allow centralized searching. Centralized security administration of intellectual property (IP) in distributed servers is enabled through the use of private/public key security tokens. Additionally, third-party reporting and analysis tools, such as Crystal Reports, are now supported through read-only SQL access to the server's data. SOAP (Simple Object Access Protocol) can be used to retrieve XML formatted data streams for custom requests, enhancing the ability to interface with other systems.
Acer Foundation and Cadence Design Systems, Inc. have announced a strategic alliance in Taiwan to cultivate talents in analog and mixed-signal circuit designs, with an emphasis on system-on-a-chip (SoC) design. At the same time, Acer has announced the inauguration of Aspire IC Design Institute, a unit within the Aspire Research Complex located in Taiwan. The institute will focus on IC designs for wireless and networking communications. Acer Foundation is a non-profit organization backed by Acer Inc. and assists industries in establishing core competencies. Both Cadence and Acer are moving to cultivate Taiwanese talents in analog and mixed-signal circuit design. Cadence will provide experienced trainers to conduct classes, field application engineers to assist the students, and teaching materials. Classes will begin in January 2003, with the capacity to take 30 students for each three-month term.
Actel Corp. announced the availability of new Advanced Encryption Standard (AES) and Data Encryption Standard (DES) IP cores optimized for Actel's nonvolatile Axcelerator, ProASIC, ProASIC Plus, RTSX-S and SX-A FPGA architectures. Through Actel and its partners, Amphion Semiconductor, Inc. and Helion Technology, customers now have access to design services and a range of encryption cores certified by the National Institute of Standards and Technology (NIST) that support AES, DES and triple DES (3DES) algorithms to help safeguard against reverse engineering, cloning, and overbuilding.
Artisan Components, Inc., a provider of semiconductor IP, announced the immediate availability of simulation views for a suite of library products optimized for Taiwan Semiconductor Manufacturing Company's (TSMC's) Nexsys 90-nanometer (CLN90G) process technology. As part of Artisan's Free Library Program, licensed customers can download these products from Artisan's website at no charge.
Artisan's suite of library products, developed under terms of an on-going agreement between Artisan and TSMC, include Artisan's SAGE-X Standard Cell Library, memory generators for single- and dual-port SRAM, single- and two-port register files and diffusion programmable ROM. The products are fully compliant with TSMC's 90-nanometer design rules, characterized using TSMC's latest electrical models and include support for Artisan's set of simulation views and physical design models of the leading EDA tools.
Cadence Design Systems, Inc. announced the completion of its purchase of the assets of Antrim Design Systems, Inc., an analog design tool provider. This purchase involves the hiring of Antrim's core R&D, sales and support team. The Antrim technology adds analog prototyping and behavioral characterization and modeling support to Cadence's existing roadmap. Cadence management announced that Cadence continues to pursue strategic acquisitions, despite trying economic conditions. Antrim's current products include Aptivia, which provides automated analysis, optimization, characterization and verification, and DCM, which provides characterization and modeling.
Denali Software, Inc. announced that its Databahn memory controller cores are used in Azanda Network Devices' Scimitar AZ61100 OC-48 Traffic Manager/ATM SAR. Azanda configured the on-chip Databahn memory controllers to provide 400 MHz data transfers from DDR-SDRAM memory devices operating at 200 MHz. Azanda's Scimitar chip performs traffic management and ATM segmentation and re-assembly functions at full-duplex OC-48 speeds, delivering a total aggregate bandwidth of 5 Gbps. The Databahn memory controller allows designers to customize a memory controller core to meet performance and interface requirements for their ASIC application. Deliverables include: RTL and synthesis scripts, verification testbench, static timing analysis scripts, programmable register settings, and documentation.
Mentor Graphics Corp. and Genesys Logic announced a technology collaboration for an integrated physical layer (PHY) and controller solution for USB 2.0-compliant applications. This collaboration provides a solution that includes high-speed function-to-host connectivity, on-the-go support for function-to-function communication, with a fully integrated PHY suitable for highly integrated chips used in consumer products. The Genesys Logic GL800 USB 2.0 physical layer transceiver integrates high-speed, mixed-signal circuitry to serve as the interface between the high-performance USB controller and the 16-bit SIE bus. The USB 2.0 Transceiver Macrocell Interface (UTMI)-compliant transceiver handles the low level USB protocol and signaling, which includes features such as data serialization and de-serialization, bit stuffing, and clock recovery and synchronization. The combination of the Mentor Graphics controller with the Genesys PHY addresses cost-sensitive consumer products by integrating both functions into a single chip.
Open Core Protocol International Partnership (OCP-IP) announced that Accent, a joint venture between STMicroelectronics and Cadence Design Systems, is joining the organization. The addition of Accent enhances an already significant European presence for OCP-IP. Recent European members joining the organization include Amphion Semiconductor, Siroyan, VCX, and Valiosys. "We are pleased to have Accent among our members," said Ian Mackintosh, President of OCP-IP. "OCP-IP's rapidly expanding membership roster shows OCP has quickly become the industry standard socket. It's a socket everyone can use, no matter their on-chip architecture or processor cores."
Additionally, OCP-IP announced that Verisity Ltd., a supplier of tools and methodology for functional verification, has joined the organization. Mackintosh also commented on the Verisity membership: "We are delighted to have Verisity's support for the industry-standard socket and believe it will help spread the benefits of verification reuse throughout the industry."
OCP-IP offers a complete socket solution to its members including tools, training and technical support necessary for creating intellectual property (IP) cores which are OCP-compliant and ready for SoC integration with other third-party IP.
Synopsys Inc. and Avnet Cilicon, a division of Avnet, Inc., announced an agreement to jointly promote Synopsys' FPGA Compiler II for synthesis of complex FPGA designs. The Synopsys tool is now a part of Avnet Design Service's Avalon Reference Design System. Avnet customers will have access to features in FPGA Compiler II, including block-level incremental synthesis (BLIS) and re-timing.
Xilinx Inc. announced that it is shipping the System Generator for DSP tool v.2.3. The System Generator for DSP tool automatically translates DSP systems developed using MATLAB and Simulink from The MathWorks into optimized VHDL and IP cores for Xilinx FPGAs. The new tool gives designers access to pipelined embedded multipliers using pre-placed input and output registers to achieve improved performance per area of silicon. The new release also supports 3x faster code generation, a dozen-plus reference designs/tutorials, and application notes for creating custom DSP data path peripherals for the IBM CoreConnectbus architecture
Toshiba America Electronic Components, Inc. (TAEC) announced the opening of its seventh U.S.-based design center located in San Diego, CA. The new design center will provide SoC design implementation support and is the second design center opened by the company this year. "Despite being in the midst of a semiconductor recession, we are committed to the SOC business and continue to invest strategically as part of our plan to grow TAEC's share of the North American market," said Richard Tobias, Vice President of the ASIC and Foundry Business Unit at TAEC. Earlier this year, TAEC opened a new design center in Minneapolis, MN, concentrating on mixed-signal development and design implementation for customers across the United States.
Coming soon to a theater near you
2002 ACM/IEEE International Workshop - If you're quick, you can still make it to the 2002 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems at the Doubletree Hotel in Monterey, CA, December 2nd and 3rd. Sponsored by ACM/SIGDA in cooperation with IEEE, with additional support from Cadence, IBM, Intel, and Magma, this year's theme is timing and deep-submicron effects in design automation. The conference includes eight sessions during the two-day conference and three additional invited sessions covering timing, design for manufacturability, and emerging technologies. The keynote address, "Computers without Clocks," will be given by Ivan Sutherland, Vice President and Fellow, Sun Microsystems Laboratories. Sutherland will discuss design and methodology considerations surrounding asynchronous design.
Accellera Seminar - There may be a free lunch after all, at least if you're a member of Accellera. On Thursday, December 5th, you can attend a free seminar for Accellera members at the Santa Clara Marriott - Accellera's Verilog Evolution: An Introduction to SystemVerilog - featuring presentations and tutorials on assertions methodologies from Mentor Graphic's Dennis Brophy, Stu Sutherland of Sutherland HDL, Infinion's Vassilios Gerousis, and Synopsys' Stephen Meier. The all-day event runs from 8:30 AM to 3:00 PM and includes, along with lunch, an EDA Vendor Fair. The conference is sponsored by Synopsys, Mentor Graphics, and Real Intent. Registration information lives at www.accellera.org/systemver.html.
edaForum02 - If you're in Germany in the next several days, you'll be able to catch edaForum02 as it convenes in Hanover on December 5th and 6th. The conference is organized by the edacentrum as part of its mission to overcome the design gap by collaborative actions of system and semiconductor companies, EDA vendors and research institutes. In contrast to pure technical workshops, this event will focus on technical challenges and business-related topics helping to optimize the EDA investment. The keynote address will be given by U.C. Berkeley's Richard Newton.
DesignCon 2003 - It's not too soon to be penciling dates into next year's calendar, starting with DesignCon 2003 from the International Engineering Consortium, running January 27th to 30th at the Santa Clara Convention Center. The conference will include the NanoEngineering TecForum on Monday, the 27th and keynotes from NVIDIA's Chris Malachowsky and Semiconductor Research's Ralph Cavin. Conference organizers will present an Executive Forum: "Leadership in Times of Change." Two tracks, one on SoC design and one on high-performance systems, will be operating simultaneously at the conference and the exhibition hall is always a great place to explore.
DATE 2003 - Also for next year, don't forget DATE 2003 in Munich, Germany. The conference runs from March 3rd to 7th and includes tutorials, master courses, an Embedded Software Forum, a Designers Forum, and sessions highlighting emerging topics in electronic design: scalability trends, security in ambient intelligent applications, test, automotive applications, run-time reconfigurable systems, network processing and RF design for highly integrated communication systems. Two items of particular interest - a tutorial on design-and-test challenges beyond 90 nm and a PCB symposium. The Program Committee reviewed 600 submissions in choosing the papers and presentations for the technical sessions. Conference organizers report that despite difficult conditions in the global electronics market, over 100 companies will be exhibiting including the leading vendors of EDA and DFT tools.
Newsmakers
1st Silicon announced that the company's board of directors has appointed Dr. W. John Nelson as CEO. Nelson, who joined 1st Silicon as COO in May 2002, has been acting CEO since September. He succeeds Claudio G. Loddo. Previously, Nelson was COO of General Semiconductor, President of General Semiconductor's Asia-Pacific operation, and President of General Instrument, Taiwan. He directed the construction of the company's manufacturing site in Tianjin, China. His experience also includes wafer-fab operations at Unitrode and Fairchild Semiconductor, and wafer-fab engineering at Analog Devices.
InTime Software, Inc. announced that Ron Burns has joined the company as Vice President of Worldwide Sales. Burns brings a lengthy track record in electronics and EDA to his new role at InTime. His experience includes sales management positions at Forte, Quickturn (A Cadence company), NeoCAD, Mentor Graphics, Silicon Compiler Systems, and Harris Semiconductor. Most recently, Burns served as Vice President of Sales at Forte where he and the CynApps executive team completed the merger with Chronology.
In the category of ...
Women's work
These days, women and men labor side-by-side in the kitchen to prepare the annual Thanksgiving feast. In honor of Thanksgiving, it seemed intriguing to do a quick, unofficial tally of the number of women currently serving in senior executive roles at fourteen of the leading companies in EDA - statistics tabulated from a simple visit to each company's website.
The results - 4 companies with 0% women execs, 4 companies with 8%, 2 companies with 16 %, 2 companies at 20%, 1 company at 25%, and 1 company at 33% - not too impressive, but there may be reasons why.
First, women rarely major in Computer Science, one of the principle feeder disciplines steering people into leadership roles in EDA. U.C. Berkeley reports that among their current crop of graduate students in Computer Science, approximately 15% are women. Stanford numbers appear to be in the 10% to 15% range and Carnegie Mellon weighs in at 22%. Also, even if women do major in technical fields, they may not consider careers in EDA because the industry is neither widely known nor widely discussed within academia. Finally, women may shy away from start-ups such as those in EDA, preferring the salary and benefits security of larger companies. For whatever the reason, the pipeline is not there and it's probably inappropriate to expect an increase in the number of women executives in EDA over the next few years.