The main campus of the University of Michigan is mighty impressive, as it would have to be to accommodate upwards of 38,000 students pursuing over 200 different academic majors. It's a great campus, complete with imposing clock tower, large central quad surrounded by layers of traditional Mid-Western College architecture, a cathedral-like law library with what has to be the most beautiful reading room in the nation, and a massive medical school complex, all integrated into that most quintessential of college towns, Ann Arbor. Michigan also has a dynamic new university president, a student and faculty population diverse in ethnicities, nationalities, and attitudes, and a vibrant sense of intellectual freedom and curiosity.
But to the jaundiced eye of the visitor seeking out the EECS Department, the main campus pales in comparison to the North Campus, a short two-mile shuttle ride away. The North Campus, looking less like a Mid-Western College and more like a New Age Industrial Park, spreads discretely across gently rolling hills and is home to the School of Music, the Gerald Ford Presidential Library, the School of Architecture and Urban Planning, Art and Design, and the Engineering School complex - which includes a clock tower of its own that's more rocket ship than time piece, a host of stylishly designed buildings to house the 11 distinct engineering departments within the school, and the creatively conceived Media Union [library] that services all schools on the site.
The North Campus is a complete world unto itself, so removed from the hodge-podge of the Main Campus/Ann Arbor confluence that it almost seems monastic in its remoteness. One gets the impression that you can live there, eat there, study there, do research there, and live out your days in peace amidst like-minded thinkers.
Or so it seemed to me when I visited the campus 3 weeks ago on a bitterly frigid day when the temperature outside never went about 34 degrees and sleet and freezing rain added to a visitor's woes. Inside the various buildings of the Engineering Complex, however, all was well and good. Particularly in the EECS building, which has its own indoor avenue, park benches, streetlights, and trees.
It was upstairs in the EECS building where I was able to talk with Professor Dennis Sylvester and to learn that he has gone full circle from a BSEE at Michigan, to a Ph.D. in EE at U.C. Berkeley, to a year in R&D at Synopsys, and back to Michigan again, where he is now Assistant Professor in EECS with an emphasis on VLSI design.
He's really enthused about the upward trajectory of the EECS Department at Michigan, and it's clear that the rest of faculty is right there with him. Sylvester told me that between Interim EECS Department Chair Richard Brown, founder of the DAC Student Design Contest, and EECS Associate Professor David Blaauw, DAC 2003 Panel Chair, there's high profile leadership in the department for VLSI design and associated research.
Sylvester said the program is further strengthened by close ties with industry. “We really like our VLSI program, but we want to be sure that everyone is on the same footing. In general, when companies hire graduates fresh out of school, they assume the graduates don't know anything and must be retrained. This is particularly true in the case of custom IC design. Here at Michigan, we work to get feedback from cutting-edge design houses to help ensure that our students receive training that will be relevant to their careers immediately upon graduation.”
“Additionally, we interact with companies like Intel and IBM to give our grad students a chance to do a large chunk of their dissertation work at an industry site - as long as the companies are amenable to having the work published, of course. It doesn't benefit a graduate student to be working on a proprietary project. Intel and IBM have been very good about donating money and equipment to our program, things that are really important to us.”
Sylvester said that Brown, Blaauw, and the entire faculty are pushing to make the department strong across all aspects of design - digital design, mixed-signal design, RF design, and EDA tools and methodologies. “With our close ties to industry, our move to hire additional faculty in analog and mixed-signal design, as well efforts to hire instructors with expertise in EDA tools, we're working to provide the curriculum in VLSI design that people really want. And we're going to be making an impact on the industry. We're definitely developing a lot of critical mass here in our program. Critical mass is hard to attain - schools like Illinois, Berkeley, UCLA, CMU have it - but we're well on our
way to having it as well. If I had to go somewhere to study VLSI design, I'd consider Michigan right alongside those other schools.”
Michigan is a school that encourages their students to publish, Sylvester said. “At the graduate level, a Ph.D. here requires 4 semesters of course work and, of course, research and a thesis. I encourage my students to stretch those courses out over 2 to 3 years, so that they can start in on their research as soon as possible - and therefore publish something as soon as possible. It can be discouraging to be just starting your research after 2 years in our Ph.D. program, while you see others around you who have already published.”
“Meanwhile, the DAC Student Design Contest comes out of Richard Brown's Student Design Contest here at Michigan. It's been a great way to generate interest in design for our students. We always impress on our students that there's a lot of activity around DAC and you just have to be there. This year our department will have 13 papers being presented at DAC, almost all by students.”
Michigan keeps an eye on student presentation skills, as well, according to Sylvester. “While we encourage our grad students, and our undergrads, to publish their research as soon as possible, we also work with them to develop the presentation skills they need to present their work at technical conferences. And of course, we encourage them to attend as many conferences as possible over the course of the year.”
Sylvester acknowledged the perception among Michigan students that they're at a geographic disadvantage. “The downside of travel for our students is that sometimes they feel isolated here in Michigan. Our grad students might go to a conference in San Jose or Monterey or L.A., and get the somewhat artificial sense that those places are where it's all happening in technology. But they're getting a warped view at those conferences, because they don't see that when the conference is over, everybody goes back to somewhere else.”
Meanwhile, at both the graduate and undergraduate level, students at Michigan have access to hands-on experience working in the fabrication facility on the first floor of the EECS building. “Our students have a chance to test out their designs by fabricating their chips. Our CMOS capability downstairs is at a micron, but we've got access to 0.18 micron if we outsource to MOSIS, or 0.13 micron through our partnering with IBM and Intel.”
Sylvester added, “We also use 'predictive' 65-nanometer models from the Berkeley Predictive Technology Modeling (BPTM) project. I started on this project at the tail end of my studies at Berkeley, and I'm happy to see a lot of universities around the country using these models. Usually universities can't get access to really advanced models, pre-production - and that was the point of the BPTM project, to allow for advanced circuit design to be undertaken at engineering schools.” As a last note, he said that the first floor fab at Michigan also provides extensive research facilities for students interested in GaAs, opto-electronics, and MEMS.
Sylvester said the department keeps a close eye on the post-graduation success of their students and he maintained that, despite reduced hiring across the industry, there are lots of openings for engineers with the specific VLSI skills being taught at Michigan. “Intel has said, 'We have 100 openings in logic development. Give us the people we need.' Clearly, it's not really true that people aren't hiring.”
Additionally, Michigan encourages students to consider careers in academia, according to Sylvester. “We don't have to do a lot of work bringing kids back into academia to teach after they've studied here. Of course, I wouldn't want all of my students to go into academia, or all of them to go into industry. We try to give them a really good experience no matter where they're headed. Certain personality types are just better suited to research and the idea of teaching, while others are better suited to industry.”
At that point in our conversation, Sylvester had to rush off to catch a plane to Monterey to attend a conference himself. I asked him if he was just looking for an excuse to escape the “Michigan Spring” that was making life outside the EECS building so friggin' miserable at that moment. He laughed and said, “I hear it's cold and raining in Monterey as well, so that can't be the reason I'm going.”
After Sylvester left, I took the self-guided tour of the EECS building, managed to finagle a tour of the Clean Room facilities on the first floor, and had one last cup of hot coffee before braving the cold and wet to make my way to the shuttle stop and the ride back to the Main Campus.
All told, I had a great visit and came away with the distinct sense that the EECS Department at Michigan, and the VLSI program in particular, is a young and dynamic destination for anyone wanting to study and work among the best and the brightest, and upon graduation, feel well prepared for a successful career in industry or academia. As it turns out, I'm not the only one who has this impression.
Kerry Bernstein is a Senior Technical Staff Member at IBM's T.J. Watson Research Center in Essex Junction, Vermont. He says, “I think very highly of Dennis Sylvester and his University of Michigan programs. The topics and issues they are studying are central to the challenges facing VLSI design - that of the effects of quantum-mechanical limitations to VLSI. My specific research interests are in the modeling, characterization, and analysis of deep-submicron interconnects and device technology, and the implications they have on circuit performance. I am also interested in design approaches to minimize the negative effects of device and wire scaling on VLSI systems.”
“Dennis and I use each other as technical references, and participate in each other's conferences and venues. I regularly field questions from his grad students, providing informal guidance. It is a model for the way I wish I interacted with other institutions. I visited the EECS Department at Michigan last year, presented a guest lecture, toured the department and labs, spoke with Richard Brown, and met with many of the grad students and other professors. I thoroughly enjoy my relationship with the University of Michigan, Dennis, and his graduate students. The work at Michigan is clearly on par with any of the other top-tier institutions I interact with.”
Hugh Boyd, a member of the Intel University Relations team, is equally enthusiastic about Michigan in detailing Intel's programs there. He says, “We have a great desire to work with young, aggressive schools - schools like Michigan, Purdue, and the University of Texas. We find young, fresh, open-minded faculty at such schools doing new and different kinds of things, including a mix of applied versus basic research. My group specifically funds Dennis Sylvester at Michigan and his work around EDA and CAD tools. It is our hope to bring new initiatives to life in places with young, enthusiastic faculty. Dennis Sylvester and the VLSI program at Michigan provide one of those places.”
Boyd says Intel University Relations interacts with the 15 Intel Focus Schools, schools which include the top 15 engineering programs in the country. “We get two primary things from working with a Focus School like Michigan. First of all, we get a recruiting opportunity. Though we're not doing as much hiring now as we have in the past, today it's a high-end, more targeted type of recruitment. Focus Schools get access to grants and give us recruitment opportunities in return. We hire from both CSE and EE Departments and we try to target our grants to areas of research in the University where future candidates would come from.”
“Second of all,” Boyd says, “we have an interest in research at the Focus Schools. Intel maintains separate Research Counsels to address areas like communications, computer architecture, semiconductor processing, applications development, and so forth. We provide funding to universities through these counsels. The grants range from $50,000 to $70,000 per year, renewable for up to 3 years, though the amounts vary from school to school. That amount of money should fund one student for one year under one professor. However, we don't get as much out of Stanford or MIT for that amount of money as we do from a school like Michigan. In general, we like to establish a tight link between the
professor/student team and an Intel researcher out of that particular Research Council. It helps us to monitor the research that we are funding.”
“Additionally, we assign an Intel executive - a Senior Sponsor - to be an internal advocate for a particular Engineering Department. We might, for instance, ask a school if they would consider developing curriculum that could work to Intel's research ends. The Senior Sponsor and I will come to the school and meet with 8 to 10 faculty over the course of a day or two, to find promising research or recruitment opportunities. Then the Senior Sponsor and I come back to our offices and match targeted research grants with potential grad students and their faculty advisors.”
“A lot of companies have programs like this. Investments in universities can be as simple as check writing without campus visits, or sponsoring pure recruitment lunches and presentations. Intel tries to bridge that gap with a more complex relationship. And, we encourage the schools to keep their focus at least 5 years out, just as Intel should be developing products today that are 5 years out. Of course, we would like to see things developed that actually have relevance today, as well.”
Both Bernstein from IBM and Boyd from Intel are relaxed in discussing how proprietary research initiatives are handled across the industry/university interface.
Bernstein says, “There are some proprietary restrictions on how we interact with schools like Michigan, but they have not gotten in the way as yet. I suspect at some point, we will need NDAs [non-disclosure agreements], but we have not yet progressed to that point.”
Meanwhile, Boyd says, “Some areas of research - for instance, computer architecture - tend to generate proprietary IP and we make it clear to the university that we want to have the rights to that IP, or at least be assured that no one else is going to get access to it. In areas like communications and applications, however, the grants are more like gifts, where we are looking to foster technical developments that will raise the entire industry. In that case, we certainly encourage publication on the part of the professor and student to promote dissemination of the results of their research.”
All told, you should not be surprised to see an increasing number of cutting-edge publications emerge from various aspects of VLSI research at Michigan over the next stretch of years. Currently there are upwards of 100 students pursuing graduate studies related to VLSI design and CAD tools in the EECS Department at Ann Arbor. If what we're hearing from faculty and industry sponsors is accurate, those students can't help but be among tomorrow's leaders in VLSI and EDA.
Rain, sleet, and snow not withstanding, something's going at Michigan. I think it's called critical mass.
More companies partnering with universities
Following on the article in the February 10th issue of
EDA Weekly, additional companies and organizations describe their educational outreach programs in this issue as well, programs which reflect a commitment to university education in VLSI design and CAD tool development. Hats off to these companies, and others like them, who find the energy and resources to partner with colleges and universities in fostering excellence in education and
research.
Synplicity, Inc. - “Through Synplicity's University Program, universities worldwide can obtain commercial development software for teaching and academic research purposes. Synplicity is committed to training future engineers by providing EDA tools, training materials, and textbooks that can be used within course curriculum. Synplicity's synthesis tools are being used at over 350 colleges and universities, including 15 of the top 25 U.S. engineering schools. Additionally, leading universities in India, Japan, Taiwan, and throughout Europe have added our tools to their academic programs. Carnegie Mellon, Cal Tech, Georgia Tech., Harvard, McGill University, Northwestern University,
Pennsylvania State University, Rensselaer Polytechnic Institute, Rice University, Rutgers University, University of New York, U.C. Berkeley,
UCLA, University of Central Florida, and University of Toronto are among the schools using our software for teaching and academic research.”
Synopsys, Inc. - “Synopsys is committed to providing educational institutions with the tools and technology needed to develop a well-trained workforce and meet the difficult challenges of IC design. The Synopsys University Program provides universities worldwide with EDA tools and technology to support teaching and academic research, to foster innovation, and to promote careers in EDA. The program helps engineering students receive hands-on experience in the classroom and in graduate-level research programs. To date, thousands of graduates have benefited from the Program, developing the skills needed to produce the next generation of complex IC and SoC designs. The University
Program provides a comprehensive, low-cost tool package for teaching and for research. In addition, Synopsys tool training workshops are available to professors at any Synopsys training center. Universities are supported through our Customer Support Center, as well as the staff of the University Program. On-line documentation and access to Synopsys web-based support services are also available. To date, the Synopsys University Program has partnered with more than 600 universities and reaches thousands of students and professors each year. Program partners include nearly all key universities in the U.S., including U.C. Berkeley, Stanford, MIT, and Carnegie Mellon University.”
IMEC - “IMEC's Microelectronics Training Center (MTC) in Leuven, Belgium, offers a broad spectrum of courses covering a wide field of micro- and nanoelectronics, microsystems, and even related fields such as biotechnology. The courses vary from high-level design issues for ASICs and microsystems, to process and packaging technology, and target engineers, managers, technicians and operators. MTC is able to build on IMEC's experience in industrial training, as well as on the available know-how and infrastructure. IMEC's clean room, its deep-submicron pilot line, its measurement infrastructure, and its design labs are equipped with state-of-the-art EDA tools. There are courses
on fixed schedule and courses on demand. Often IMEC accepts residents for longer periods, for on-the-job-training in joint R&D activities. The MTC plays an important role by training teaching staff of high-schools, polytechnic schools, and universities.”
Icinergy Software Co. - “There is a somewhat limited amount of research going on in Canada in EDA. To assist in fostering more EDA research, we have been actively supporting our education system by way of the employment or participation of students. We have had through our short history, graduate, undergraduate, and high school students actively involved in the development of our software. Through contact with CMC (Canadian Microelectronic Corporation) and SMC (Strategic Microelectronics Council), we have been able to put forward joint proposals for Canadian research funds to work with people like Professor Zhu of the University of Toronto. [Please see below.] Working with
Professor Zhu has the advantage of directing research that focuses on projects with a direct application to commercialization. Our product has been used at 5 different universities in Canada, and we are currently working on 3 different projects at 3 different universities.”
Forte Design Systems - “Forte established an informal university program in 2001. Since then, we have been working with interested universities to provide them with access to the latest technology in behavioral synthesis. Selected universities receive access to Forte's technology in exchange for feedback on the tools and methodology and design examples. In addition, we require publication of at least one technical paper within the calendar year. In 2003, we will be formalizing this program as we open it to more universities.”
CoWare Inc. - “CoWare has an active university program. The company's System Level Design and LISATek tools have academic roots, and the company has an ongoing relationship with and commitment to support education and research. CoWare has close partnerships with key universities around the world, with a high return on investment, which includes outstanding hires, advanced technology breakthroughs, and industry leadership. The CoWare Technical Advisory Board, with Stanford University and ISS members, provides ties to research teams. Japanese universities now patent university inventions prior to publication of academic papers, thereby acknowledging the importance of academic research.
This research is shaping how customers develop their product roadmaps, and CoWare is always interested in working with key universities that support customers in Japan. Finally, CoWare has and continues to benefit from university ties. The company is currently expanding university offerings to include LISATek and SystemC solutions in all key markets.”
Celoxica - “The Celoxica University Program (CUP) was established in 1997 to encourage research and teaching using Celoxica products and technology for software-compiled system design and reconfigurable computing. Through the CUP, the full commercial DK Design Suite is delivered at minimum price levels and augmented by heavily discounted FPGA hardware platforms for teaching and research. The company's website provides an on-line knowledge base, courseware, source code IP downloads, and other materials to CUP members. Celoxica software-style methodology for hardware design allows students to produce interesting applications that can be implemented in real hardware.”
“The University of Essex (UK) has demonstrated that foundation hardware-software co-design skills can be acquired in 2 days by students with limited previous hardware background knowledge. At the Imperial College of Science, Technology and Medicine (UK), first-year students are able to produce complex FPGA designs such as image and graphics processing. And at the Indian Institute of Technology Mumbai, part of their Distance Education Program is broadcast by satellite to a large number of registered Remote Centres, which are equipped with Celoxica's co-design simulation tools for use during student laboratory sessions. Celoxica was founded on technology originally from Oxford
University. As such, we view the CUP as one of our best strengths. CUP has over 700 active members around the world and the company uses this feedback to improve our products. Of course, support is a concern, as that many universities with undergrads could easily swamp a small company with support requests. We handle this by developing relationships with professors who use our products in research and course work. They in turn manage the support 'burden.' Celoxica benefits from the research and from the large installed base of DK-trained engineers coming out of academia.”
Axis Systems - “Axis Systems' University Program is focused on research groups in Asia/ Pacific, whose current research is developing improved verification flows. This regional concentration allows us to gain early penetration in a growing market. We provide RCC-based (Reconfigurable Computing) Xcite systems with support and training. Axis was originally approached by Dr. Allen Wu at National Tsing Hua University in Taiwan because he had difficulty in acquiring software from other EDA companies who were worried about piracy. Since Axis' tools contains a hardware component, we are not as concerned with privacy. The Universities benefit from the use of the latest verification
technology, and we profit from the introduction of the RCC platform to the brightest engineering graduates, while earning their positive endorsement.”
Aptix Corp. - “Universities throughout the world are invited to participate in Aptix' University Program. Under this program, universities gain access to Aptix hardware and software products for use in teaching and non-commercial research projects. Key elements of the program include discounts on new hardware, occasional special pricing on used hardware, software at no charge, and special university rates on maintenance. To qualify, universities must have a sponsoring faculty member, use the equipment in teaching a course, publish a paper describing a research project in which the equipment was used, write a white paper or application note describing a novel use of the equipment,
or submit prototyping IP to the Aptix IP Library. Participating universities include Purdue, Morgan State, University of Munich, and Chengdu University.”
Ansoft Corp. - “Our Student Version (SV) program has about 50 schools with have over 200 copies of our software installed, or in use for course work. This number doesn't include the 100s of other schools that have 25 to 50 copies of our software installed. Ansoft has donated multiple copies of software to Virginia Polytechnic University in exchange for sponsorship in the CPES Consortium (Center for Power Electronics Systems). We have donated multiple copies of software to Portland State University in exchange for sponsorship in the Portland State Aerospace Society (PSAS), and have also donated software to IIT in exchange for sponsorship of the Illinois Institute of Technology
2003 International Fuel Energy Challenge Team. We provide sponsorship of the Berkeley Wireless Research Center where HFSS has become an important part of their tool suite for the design of 60 GHz CMOS and Ultra-Wideband design work. Finally, Bangladesh University of Engineering Technology has been quoted as saying that all the Ansoft tools have very good user interfaces and examples to help students and teachers get started. These additional capabilities provide very good scope for research.”
Alternative System Concepts, Inc. (ASC) - “ASC has had excellent experience with universities as EDA business partners. Our two-pronged partnerships include employment and subcontract research. In appreciation, we repay universities through the ASC University Grant Program, which provides our tools for use in educational research. There is no charge for the license; the only charge is for annual maintenance. ASC employs student interns during the summer and extended class breaks. Cooperating universities include MIT, Tufts, University of Massachusetts, Dartmouth, University of New Hampshire, and Arizona. We typically assign undergraduates to new development tasks, where they
can work at their own pace with their own creative talents. We treat them as part of the team and instill in them a sense of mutual trust. The biggest problem with student interns is inadequate documentation. Students, besides being bright and ambitious with a good work ethic, are uncorrupted by industry influences. The other partnership with universities is through research. The DoD Small Business Innovation Research program allows ASC to compete for contracts and grants as a small business, and subcontract research to a university. Much of the EDA technology that forms the basis for ASC design tools was developed jointly by ASC and major universities, including Princeton, Polytechnic, UMASS, Northeastern, Virginia, and New Hampshire.”
Aldec Inc. - “The Aldec University Program (AUP) is dedicated to the support and continued improvement of higher education by offering commercial software, training, and support at little-to-no cost for qualified universities and research institutes worldwide. Aldec's University Program was established in 1996, and has grown to over 1000 university and research institutes by providing network software licenses for campus-wide access, starting at less than $200, and personal 'Student Editions' of the software for less than $60. The educational network software
licenses have no feature limitations, but may only be used for educational and/or research purposes within an accredited
university program. AUP includes access to the licensed software and benefits such as departmental training, product updates, technical support including hands-on-tutorials, and product documentation. In addition, Aldec is actively involved with on-campus corporate sponsorship including classroom training, keynote lectures, and student internships. A few of our current AUP members include MIT, UCLA , the Naval Post Graduate School, Cal Tech, Osaka University (Japan), Bristol University (UK), ISS College of Engineering (India), and Kiev Technical University (Ukraine)”
The University of Kansas speaks about Accellera - “The Accellera EDA Standards organization has successfully interacted with the University of Kansas to begin standardization of the Rosetta systems-level requirements specification language. Together with Titan Systems, The University of Kansas developed the Rosetta specification language in response to industry and government needs for systems-level specification. However, universities are not well equipped to carry their research results through to industrial use. Accellera provides the needed expertise and resources for industrialization and standardization. Recognizing the importance of standard languages at the
systems level, and the potential for Rosetta, Accellera licensed the rights to Rosetta from the University of Kansas. Accellera is sponsoring standardization efforts and provides valuable industry inputs. Working with Accellera helps assure that academic research efforts address industry needs and result in viable industrial products.” (The comments of Dr. Perry Alexander at the University of Kansas.)
Closing comments and kudos from the University of Toronto - “There are generally two types of interaction we have with industry. One type of interaction applies to undergraduate teaching where we use EDA tools, typically from major EDA vendors, in the lab portion of our courses. Those tools include electronics (HSpice from Avanti), digital logic (MaxPlusII from Altera), and VLSI tools (Synopsys and Cadence). Our primary goal here is to help students better understand the concepts taught in class. Our goal is to make sure that when the students go out to industry, they already have experience with the most popular tools. One common problem we have here
is, the vast number of different options offered by the EDA tools often obscures the basic design flow. While this is favored for sophisticated designers, it is sometimes not convenient for teaching and we often have to create scripts to get around it. It would be nice to see 'education-friendly' packaging of the EDA tools, especially from the major vendors.”
“A second type of interaction typically applies to graduate teaching and, depending on topic, we often work with start-up companies who offer advanced point tools. For example, I have used the SOCarchitect from Icinergy for high-level design planning and eXCite for high-level synthesis from C. We appreciate very much the fact that the EDA sector has always made the effort to invest in education. It is interesting to note that the investment from the EDA industry is very disproportional to its market size, compared to investments from other sectors of the semiconductor industry.” (These comments were received from Dr. Jianwen Zhu at the University of Toronto)
Industry News - Tools & IP
Accelerated Technology, the Embedded Systems Division of Mentor Graphics Corp. announced the initial availability of Nucleus USB, which provides Universal Serial Bus support for the Nucleus RTOS. The company says this combination of real-time software “makes it easy for developers to quickly create embedded systems that communicate over USB.” The Nucleus USB family consists of embedded software to host (or connect to) various USB devices, create USB devices, and drive USB hardware controllers.
In related news, the company announced the initial availability of Nucleus Simple Network Management Protocol (SNMP) version 3. Nucleus SNMPv3 is an embedded implementation of the SNMP version 3 protocol. Finally, the division announced the availability of the Nucleus NET embedded TCP/IP protocol stack for networking developers using the micro-ITRON specification. This release of Nucleus NET allows micro-ITRON users to develop their networking application with a source code, royalty-free software solution. Clearly all of this news was timed to coincide with the Embedded Systems Conference in San Francisco this past week.
Meanwhile, from Mentor Graphics - The company introduced a USB software stack purpose-built to complement its line of On-The-Go (OTG) controllers. The Mentor Graphics Inventra Dual Role Controllers support both the host and function capabilities of a device and the ability to swap those roles dynamically. The software stack has been tuned for small footprint and power efficiency. Target applications for USB OTG include digital cameras, PDAs, and mobile phones.
Also from Mentor Graphics Corp. - The company announced the availability of the IP-Xpress Target Platform, which allows designs - including fixed IP such as microprocessor and DSP sub-systems - to be verified with the Mentor Graphics emulators. The company says the product builds on a range of proven microprocessor and DSP boards, and is the latest addition to the Mentor Graphics iSOLVE tools for embedded processor verification.
Axis Systems, Inc. announced that its products now support the Linux open source operating system, which the company says creates the first complete Linux-based hardware acceleration and emulation systems.
Agilent Technologies Inc. announced three new DesignGuide utilities and a new application guide in its ADS 2003A EDA software. The company says the features are tightly integrated into ADS 2003A to help
power-amplifier design engineers by automating many “time-consuming steps” in the design process. The Transistor Bias utility improves design flow by automating the biasing of Bipolar, MOSFET, and GaAs devices. It automatically extracts transistor DC parameters and synthesizes an appropriate network to achieve a given bias point. The resulting transistor performance is verified and displayed graphically.
The Smith Chart and Matching utilities automatically synthesize matching networks. The Smith Chart's graphical user interface allows the designer to create a matching network topology and watch the frequency response in real time. The Matching utility allows for both narrow-band and broadband matching. The Matching software transforms a matching networks' lumped components, to ideal transmission lines and microstrip elements. The Load Pull application guide allows designers to import load-pull data from Focus Microwave and Maury Microwave load-pull systems. The scattered data interpolation is used to generate load- and source-pull contours for measuring multiple parameters
simultaneously. This data can then be used with impedance matching to synthesize matching networks.
Bookham Technology plc has migrated its MMIC model and design libraries to the latest release of Agilent Technologies' ADS 2003A. Under an early adopter program, Bookham says it has been working with Agilent to improve the finished software and to ensure a smooth transfer for its customers who will be using the new release in the “near future.”
Beach Solutions announced that its EASI-Studio 3.0 is making its “formal debut” in the U.S. market. EASI-Studio 3.0 is part of Beach's EASI-Tools family for “packaging IP and ensuring the consistency of design data through the development process.” The company says the requirement for consistent data flow is becoming increasingly important as IP complexity and SoC design challenges continues to escalate. EASI-Studio 3.0 locates captured IP blocks into a system using a bottom-up methodology, while it captures multi-layer systems using a top-down approach to systems building.
The company says both methods have been designed to integrate into existing SoC development processes. EASI-Studio 3.0 is based on the XML database format and permits design engineers to define complete system architectures that include multiple buses, transaction ports and IP block interconnections. By capturing the port information for an IP block using the EASI-Studio GUI, a design engineer can locate the block in a multi-layer system. Before any generation takes place, all captured data is checked against in-built and user-defined rules.
Cadence Design Systems, Inc. announced it has successfully ported its design-for-test (DFT) software to Advanced Micro Device's new AMD Opteron processor and AMD64 architecture. The company reports that, earlier, Cadence DFT tools had been used in the AMD Opteron processor design methodology.
Also from Cadence - The company announced the “next step” in its alliance with Xilinx Inc. will include complete support for the new Spartan-3 platform FPGAs, which were announced April 14th. - a step numerous other companies have taken as well. The Cadence Incisive verification platform and chip-package-board tools optimize the “design chain link between Xilinx and its customers by enabling the rapid design, verification, and PCB implementation of the Spartan-3 platform.” Additionally, Cadence says its tools were used throughout the Xilinx design process to deliver what is being described as “the industry's first 90-nanometer FPGA.”
And this from Synopsys - The company announced that its VCS HDL simulator will support the AMD Opteron processor-based Linux platforms for verification of SoC designs. The company says VCS simulation on hardware platforms containing the AMD Opteron processor and running the 64-bit Linux operating system, will provide engineers with the performance and capacity needed to verify next-generation IC designs. For the development of the AMD Opteron processor, AMD says it utilized VCS in an AMD Athlon processor-based Linux farm to achieve four billion simulation cycles per day and meet its functional verification milestones.
MIPS Technologies, Inc. announced at the Embedded Systems Conference (ESC) in San Francisco that the updated version of the Microsoft Windows CE .NET operating system, version 4.2, includes support for 32- and 64-bit MIPS-based microprocessors. Formerly code-named “McKendric,” the company says the update to Windows CE .NET features faster performance and real-time processing, richer multimedia and Web browsing capabilities, and greater application compatibility across Windows CE-based devices. No mean feat. Both companies says they have been working together closely since the inception of the Windows CE operating system.
In February 2003, nine MIPS Technologies licensees including AMD, Broadcom, PMC-Sierra and Texas Instruments, as well as MIPS and Microsoft, announced the “MIPS Alliance for Windows CE.” MIPS says the Alliance is a “multi-company effort to help make the industry-standard MIPS architecture and the Windows CE .NET operating system the technologies of choice for OEMs developing next-generation digital consumer devices.”
Monterey Design Systems announced that Ricoh Co. Ltd. has purchased the entire line of Monterey planning, prototyping, and implementation tools for immediate use in Japan. Ricoh says its decision to choose Monterey for their hierarchical design flow was based on results achieved on a 10-million gate hierarchical SoC design. Ricoh also says that the Monterey Progressive Refinement methodology delivered an “optimized top-level design plan and accurate physical prototypes of all twelve top-level blocks and of the top-level assembly in just over 25 hours.”
LSI Logic Corp. and Synplicity Inc. announced a joint development, marketing, and distribution agreement to provide an optimized physical synthesis tool expressly for LSI Logic's RapidChip customers. Synplicity says it is working closely with LSI Logic's RapidChip engineering team to create a customized physical synthesis solution that targets the RapidChip architecture to “set a new standard for custom logic designer productivity. The result of this joint development will be a new class of physical synthesis tool that enables designers to readily achieve design goals on RapidChip products.”
As part of the agreement, LSI Logic will also license the jointly developed physical synthesis product for internal use. Synplicity is developing a custom physical synthesis and mapping tool that will allow RapidChip customers to reach placement-based timing closure of high-density, high-performance designs.
Synplicity expects its customized physical synthesis product to be available for RapidChip customers in Q3 2003. Synplicity and LSI Logic are working together to train their field application engineers and design centers on the new product. In future phases of the relationship, Synplicity intends to develop
enhanced versions of the software in conjunction with LSI Logic, to integrate the latest design software and architectural enhancements to the RapidChip product. In a separate purchase agreement, LSI Logic has expanded their use of Synplicity's suite of FPGA and verification design tools.
Mark Nelson, Director of RapidChip Marketing at LSI, says, “Mask costs are increasing, and managing the complexity of the additional nodes available today means that the overall costs of design are rising quickly as well. Multiple sources of IP, the integration process, and the verification process are adding to time-to-design. The problems require more than just a silicon solution - they require a silicon solution plus a tool solution. Of course, there's a laundry list of problems from tool providers, as well. So, it isn't that LSI is claiming a solution or that Synplicity is claiming a solution. Neither of us alone can present a solution. In fact, we find ourselves back full circle to the
early 1990's, or earlier, when ASIC vendors developed their own tools and capabilities. It's not that we're trying to create an exclusive tool flow/design environment, but the joint development with Synplicity will offer our customers more capability, and give us netlists that are timing closed, that will predictably go through P&R quickly.”
John Gallagher, Director of Marketing for ASIC products at Synplicity, says, “Today, we're actually working to provide the tools, the flow, and the methodology that will meets LSI's capabilities. As Mark said, it's almost a vertically integrated structure once again. If you think about it, you can see that over the last 10 years a growing arms-length relationship developed between EDA providers and ASIC vendors. But, if you go back 10 years, when I was at LSI, clearly there was then a closer relationship with Synopsys and other major tool suppliers. By the mid-to-late 90's, that had changed. Now, with this partnering between LSI and Synplicity, we're seeing a move to close collaboration
once again. Of course, we don't have to go to the illogical extreme of one-to-one mapping between customer and tool vendor.”
Nelson responds, “Our arrangement with Synplicity is to optimize tools to meet the RapidChips needs. Meanwhile, RapidChip is a 'structured' ASIC and is not a replacement to FPGAs. For some, a cell-based ASIC is the only choice. For others, FPGAs at lower end of spectrum are a possibility, but unit price and flexibility present challenges there. RapidChip's applications are at the extreme high-end of the FPGA space and the bottom end of ASIC space. The goal of RapidChip is primarily to shorten time to market. The Synplicity tools will allow us to do that predictably. We're not creating an exclusive tool environment here, but certainly the Synplicity tools open up a much broader market for us.”
Gallagher concludes, “Over the past decade, Synplicity has developed close relationships, proprietary relationships, with Xilinx, Altera, and other vendors. We're doing a good balancing act here. We have a history and an ability to avoid the problems of being too closely linked to customers. At Synplicity, we've worked closely with the RapidChip designers. We can go from physical analysis - placement and congestion - and cross probe back into LSI tool. Likewise, the customer can bring things back into the LSI tool. It's a degree of interoperability that has not been seen before. Frankly, I think this joint program will bring more designs back from COT designers, and into structured ASICs.
We think the structured ASIC market is catching on in dramatic way. Clearly LSI is hitting a nerve, and we'll be providing tools and support for that effort.”
If seamless integration across the messaging from the two companies is any indication, this LSI/Synplicity collaboration should be one to watch closely going forward.
Also from Synplicity - The company has announced a strategy to develop ASIC physical synthesis technology, which combines the benefits of physical synthesis and silicon virtual prototyping into one tool environment. The company says it believes its physical synthesis technology will provide a tool for the gate-level netlist handoff market, where designers pass their designs to either internal or external organizations for the back-end design work, as well as for the emerging structured ASIC market.
Currently, ASIC designers must use two separate technologies to achieve timing closure - silicon virtual prototyping to define a floorplan that can be physically implemented, and physical synthesis to deliver a gate-level netlist along with a legal placement. The current approach has been difficult for many designers to use because of tool expense, learning curve, and differences between results that arise from two separate environments. Synplicity says that if the underlying synthesis, timing analysis,
and placement technology is extremely fast, both silicon virtual prototyping and physical synthesis can be performed together, which will result in better, faster optimizations being performed on the design.
The company says its technology can operate on the entire design at once, and perform fully automatic initial floorplanning, followed by simultaneous RTL synthesis, clock tree estimation, and placement, to deliver a physically optimized gate-level netlist for project handoff, which will in turn eliminate the need for a logic designer to become an expert in back-end design. Synplicity says it believes that “within a fraction of the time of other approaches,” ASIC designers using Synplicity's physical synthesis technology will be able to generate a final netlist and placement with high correlation to the final GDSII implementation of their design.
Palmchip Corp. announced the availability its new serial ATA target controller core. The BK-3720 core is designed to interface between a host system and a storage controller, either solid state or rotating media, optical or magnetic. The core implements transfer speeds of 150 MB/s and is compliant with the Serial ATA 1.0A specification. The BK-3720 has integrated serial ATA transport and link layer logic. It supports 48-bit sector addressing and has a 256-byte FIFO for buffering data. Additional features include buffers for incoming and outgoing packets and for ATAPI packet commands.
Synopsys, Inc. announced the most recent release of PrimeTime is improving runtime over previous releases, benchmarked on customer projects, as a result of algorithmic improvements to reporting and SDF-based (standard delay file) timing analysis.
Tarari Inc. and Celoxica Ltd. announced the release of Version 2.2 of the Tarari Content Processor Developer Kit. The companies say the new release provides enhanced capabilities to “lower development costs, improve ROI, provide quicker time to market, and increase ease of use.” The Tarari Developer Kit uses Celoxica's DK Design Suite to help developers create a hardware-accelerated version of their software. Additional enhancements to the Developer Kit include hardware performance acceleration through the ability to select multiple clock sources, and an improved interface for higher throughput.
Verplex Systems Inc. announced Conformal Datapath (DP), a new component of the company's family of formal verification products. Conformal DP is designed to verify complex optimized datapath circuitry produced by datapath and synthesis tools. The company says datapath has always been a difficult challenge for equivalence checking due to the complexity of formally verifying complex arithmetic operators, and is becoming even more difficult as EDA vendors incorporate datapath capability into standard synthesis tools. The company also says that synthesis design tools have grown so complex that an independent verification tool such as Conformal DP is needed to audit the process
by which the synthesis tools generate circuitry.
Formal verification tools that are not independent may require “side files,” data clandestinely passed from the synthesis tool, in order to verify the circuits, which in turn increases the risk that the formal verification tool uses the same assumptions that were made during the synthesis process. Conformal DP automatically verifies flat datapath modules, verifies merged operators, provides advanced pipelining, and carrysave verification. The company says that with the addition of datapath capability, the Conformal family of equivalence checking products now offers a package for “complete and independent SoC verification.'
TriCN introduced a “comprehensive” library of Base I/O cells, developed as part of a new partnership agreement between TriCN and Virage Logic Corp. Both companies will be distributing the Base I/O libraries. Initial offerings are targeted for the TSMC and IBM 0.13-micron processes, with future support planned for other foundries and geometries.
Virage Logic announced the availability of the first in a series of “silicon-proven technology-optimized” semiconductor IP platforms. The company says the platforms are intended to help SoC designers meet design challenges as the gap between technology capabilities and design productivity widens. The first Virage Logic Technology-Optimized Platform is available on TSMC's 130-nanometer process.
Rich Wawrzyniak, senior analyst at Semico, said, “With increased process and design complexity and shorter design cycles, there is a need in the market for both pre-tested and ready-to-use components that are interoperable and offer SoC designers a single-source for their IP requirements. Virage Logic is now in position, with the addition of its new Base I/O library, to offer its complete Technology-Optimized Platform to deliver cost, performance, and reliability benefits for the foundry and IDM markets.”
Industry News - Devices
Cadence Design Systems, Inc. and TeraChip Inc. announced a “major success” on a switch fabric chip running on a TSMC 0.13-micron process. Cadence provided silicon engineering that the company says “enabled” TeraChip's TCF16X10 160Gbps single-chip switch fabric design. TeraChip says the new chip is the “world's first 160Gbps scalable single-chip switch fabric targeting the LAN, SAN and MAN switch and router markets.” The TCF16X10 switches 160Gbps in a single 15W chip and integrates
64 silicon-optimized 3.125Gbps SerDes transceivers developed by Cadence Design Foundry as licensed silicon IP in the TSMC 0.13-micron process.
MIPS Technologies Inc. jointly announced numerous new MIPS-based products at the Embedded Systems Conference. Centillium Communications introduced the MIPS-based Entropia III, its fourth generation voice-over-IP processor that the company claims is the “highest density, lowest power, and most cost-effective SOC solution available on the market.” IDT demonstrated various integrated communications processors from its Interprise family - the MIPS-based RC32334, RC32355 and RC32438 processors. Intrinsity announced the FastMATH-LP device, a MIPS-based FastMATH Adaptive Signal Processor product that delivers “the highest programmable performance for power-constrained
embedded applications.” PMC-Sierra announced the Jaguar-ATX form factor evaluation board for the company's RM9000x1 and RM9000x2 highly integrated 1 GHz 64-bit MIPS-based processors. Toshiba America Electronic Components, Inc. (TAEC) made a number of MIPS-based announcements, including a new single-chip high-definition digital multimedia decoder device with an integrated 64-bit 200 MHz MIPS-based TX49 CPU, an MPEG-2 decoder and peripherals, the TMPR4938XBG-300 that operates at a maximum frequency of 300 MHz with low-power consumption and includes a built-in Ethernet MAC or a NAND Flash Memory interface, and the new TMP1962 that incorporates one megabyte of mask ROM or Flash Memory and 40 kilobytes of ROM along with various peripheral functions in a 281-pin package.
TAEC also announced a new ARM-based RISC networking controller, the company's first offering in its SoCMosaic custom chip program of SoCs. The company says the T6TC1XB-0001 was developed specifically for low-cost networking and consumer convergence applications, including access points, home gateways, small office/home office routers, thin client internet-capable devices, networked peripherals, multimedia application servers and multi-channel voice-over-IP phone sets. Customers can also use the new device as a template to design SoCMosaic custom chip derivatives.
Newsmakers
Accelerated Technology announced that it has been named the official North American Liaison Office of the TRON Association. The name “TRON” is derived from “the real-time operating system nucleus.” As an extension of the TRON Association in Japan, Accelerated Technology aims to further the Association's efforts by spreading awareness of TRON and promoting the adoption of standard specifications to the embedded market in North America.
Emulation and Verification Engineering (EVE) has signed a channel partner agreement with Monarch Technologies Group. Under terms of the agreement, Monarch Technologies Group will sell EVE's ZeBu hardware platform in the Western United States.
Cadence Design Systems, Inc. announced the Cadence SoC Encounter architecture for nanometer-scale digital IC design implementation has been chosen by readers of EDN Magazine as the EDA winner in the magazine's 2002 Innovation Awards. The EDN Innovation and Innovator of the Year awards program honors outstanding engineering professionals and products. Finalists for the awards were chosen by EDN's editors. Readers then voted to select the winner in each category. Products considered must have been introduced and commercially marketed sometime between January 1, 2002 and December 31, 2002.
PDF Solutions, Inc. announced that Michael Buehler-Garcia has joined the company as Vice President of Marketing. Additionally, former Executive Vice President of Sales, Marketing and Business Development, Dave Joseph, has been appointed Chief Strategy Officer, and former Vice President of Sales, Cees Hartgring, has been named Vice President, Worldwide Strategic Business Development and Sales.
John Kibarian, President and Chief Executive Officer of the company, attempted to clarify this round of musical chairs when he said, “We are pleased that Michael Buehler-Garcia has joined PDF Solutions as Vice President of Marketing. With significant experience in the semiconductor and electronics industries, and strong leadership qualities, Michael brings valuable perspectives relating to both the design and manufacturing of integrated circuits. As Chief Strategy Officer, Dave Joseph will develop corporate strategy, expand strategic partnerships, and ensure alignment throughout the company. In his previous role as Executive Vice President of Sales, Marketing and Business Development, Dave
guided the development of our current solutions. This new appointment will further leverage his abilities and allow him to focus on strategic issues affecting PDF's position in an evolving semiconductor landscape. In a related change, Cees Hartgring, as Vice President, Worldwide Strategic Business Development and Sales, will further expand our business globally.”
Previously, Buehler-Garcia was at Chartered Semiconductor Manufacturing, where he was Vice President of Worldwide Marketing and Business Development. Earlier, he held executive positions at Cadence and spent 14 years at Motorola. Buehler-Garcia has a B.S. in Mechanical Engineering and Energy Systems from Arizona State University.
Synopsys Inc. announced that Tom Williams has been named a Synopsys Fellow. Raul Camposano, CTO at Synopsys, said, “A Synopsys Fellow is a rare individual who has reached the highest level of technical expertise and innovation, and has applied this expertise to further his or her field. Tom has helped shape the direction of Synopsys test automation products. His expertise in the areas of DFT, test generation, fault simulation, synthesis, and fault-tolerant computing has contributed greatly to Synopsys' leadership in test automation, and has had significant positive impact on our company and on our extended community of customers.”
The company says, “This award of distinction acknowledges the contributions Dr. Williams has brought to Synopsys, the influence he has had on the company's technical direction, and the role he has played in executing and delivering design-for-test technology innovation to customers. As a member of Synopsys' test automation R&D group, Tom Williams has contributed to an impressive array of patented technologies and methodologies that have been incorporated into Synopsys' DFT Compiler and TetraMAX products,
including integration with Physical Compiler, links to test equipment to enhance diagnostic capabilities, and the recently introduced DFT Compiler SoCBIST.”
Williams has served as founder and chair for a number of IEEE and IEEE Computer Society events and technical committees. He has contributed to numerous technical books and papers in the area of test, is an adjunct professor at the University of Colorado in Boulder, and has served as a guest professor and Robert Bosch Fellow at the Universitaet of Hannover, Germany (1985-1997). He was named an IEEE Fellow in 1988 for leadership and contributions in DFT, and in 1989 was co-awarded the IEEE Computer Society's W. Wallace McDowell Award for the development of level-sensitive scan test for solid-state logic circuits, as well as for leadership in the area of DFT. Prior to joining Synopsys, Williams
was with IBM's Microelectronics Division in Boulder, CO, where he managed the VLSI Design for Testability group. He received a BSEE from Clarkson University, an MA in Pure Mathematics from the State University of New York at Binghamton, and a Ph.D. in Electrical Engineering from Colorado State University.
Tenison EDA has named VLSI One, Ltd. as its Canadian representative. VLSI One is a new company specializing in representing companies in EDA and IC technologies.
Virtual Silicon Technology, Inc. announced the company has moved its worldwide headquarters to a new location in Sunnyvale, CA. Virtual Silicon will double its office space to meet the needs of its
expanding business. The move from Virtual Silicon's previous headquarters location in Sunnyvale is effective immediately.
In the category of ...
Cooley twice over
You've got to hand it to John Cooley. He keeps the industry guessing and makes it an edgy space within which to operate. Two years ago this week, I was laid off from my job along with the majority of the Editorial and Sales staff at ISD Magazine. Several weeks later, in the midst of a phone call with John, he asked me what my plans were for DAC 2001. I told him my dad had just died, I had just been laid off, and I had neither the desire nor the energy to show up at DAC. His response was, “Cinderella doesn't not show up for The Ball. Buy yourself a ticket and get yourself to Las Vegas!” I've been grateful to John since that time, for showing me what a little courage and a lot of
huzpah can do. Having said that, here are two e-mails about Cooley that I've received in the last several weeks.
Letter No. 1
I'm on the ESNUG list, so I received John Cooley's questions today for attendees of SNUG'03 and DVcon'03, the answers to which he'll incorporate in his trip reports. The penultimate question was # 19) “See anything interesting under NDA? What did you think of it?”
To me, this falls just the other side of outrageous. What is he asking people to do? Violate a legal document? And if he's not asking them to disclose something they shouldn't be disclosing, then what can he possibly do with such vague information as “there's something interesting coming down the pike in analog layout.” And if he IS asking them to disclose something they shouldn't be disclosing, then what would he do with that information?
Letter No. 2
John Cooley wrote about an ad that's been running in EE Times that said something like “the end of synthesis as we know it.” I went and looked for it and found it - it's an all-red page that doesn't have a company name, just a website (
www.rtl2gdsii.com) that also doesn't say who the advertiser is. Do you know???? Don't keep it a secret!
(Editor's Note: I don't have answers to the questions posed in either of these letters.)