“The IEEE 1149.7 test and debug technology will allow the electronics industry to extend IEEE 1149.1 capabilities while also providing increased functionality to their embedded designs,” said Stephen Lau, emulation technology product manager, Texas Instruments (TI). “IPextreme plays an integral part in enabling rapid adoption of the technology throughout the industry. Their technical expertise and experience in working with semiconductor leaders makes them well-suited for this initiative.”
“IPextreme continues to play a critical role in providing the industry with leading technology and monetizing semiconductor companies’ R&D investments,” said Warren Savage, CEO & president, IPextreme. “Our business proposition allows us to work with a wide variety of technology leaders to produce high quality IP products. Our objective is to make both TI and our customers successful through the adoption of the IEEE 1149.7 standard.”
IPextreme’s cJTAG – IEEE 1149.7 Features
IEEE 1149.7 does not change or replace IEEE 1149.1. Instead, it offers a scalable set of extensions to IEEE 1149.1 that ensures interoperability between IEEE 1149.1- and IEEE 1149.7-based devices and test equipment. Features of the cJTAG – IEEE 1149.7 IP core include:
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Support for IEEE 1149.7 classes 0-5 (selected through hardware configuration parameter). |
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Partitioned along IEEE 1149.7-specified functional boundaries: |
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-- Extended processing unit (EPU) for class 0-3 operation. Advanced processing unit (APU) for class 4-5 operation. |
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| -- Further parameterization within EPU and APU for class-specific and optional features. | |
| -- Separate blocks for clock and reset signal conditioning. | |
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Supports all mandatory and optional scan formats: JScan0-3, SScan0-3, OScan0-7 and MScan. |
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Supports all mandatory and optional commands. |
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Firewall provides robust hot-connection by disabling test clock (TCK) until firewall is disabled by the debug test system (DTS). |
For additional information and to view the product brochure please visit: http://www.ip-extreme.com/IP/cJTAG.html
cJTAG – IEEE 1149.7 Availability and Pricing
The cJTAG -- IEEE 1149.7 product, available from IPextreme today, includes Verilog source code, integration testbench and tests, documentation and scripts for simulation and synthesis, with support for common EDA tools. cJTAG -- IEEE 1149.7 is available for $75K, list price. For ordering details, please contact your local IPextreme office -- http://www.ip-extreme.com/company/contact.html
IPextreme will be hosting a one-hour webinar in mid-September entitled, “cJTAG – IEEE 1149.7: The Next Generation in Test and Debug.” For more details and information please visit: http://www.ip-extreme.com/webinars/
About IPextreme Inc.
IPextreme packages, delivers and supports famous IP (intellectual property) designed by large semiconductor companies and used by system-on-chip (SoC) designers worldwide. These production-proven IP products serve both broad horizontal markets and specific verticals such as consumer and automotive, and are provided in a process-independent and EDA-neutral format for easy use by the widest range of customers. With a decade of experience in developing, packaging, licensing and supporting IP, IPextreme offers a complete business solution that allows semiconductor companies to strategically leverage their internal IP portfolio and expand overall revenue. The company has offices in Campbell, California; Munich, Germany; and Tokyo, Japan with representatives in China, India, Israel, Korea and Taiwan. For additional information, please visit www.ip-extreme.com.
About IEEE 1149.7
The IEEE 1149.7 standard is currently in draft and is headed for ratification by the IEEE in early 2009.
IPextreme and Core Store are registered trademarks of IPextreme Inc.
All other product or service names are the property of their respective owners. All rights reserved.
Note to editors:
A graphical representation of cJTAG interconnects and board-level topologies are available at: http://www.ip-extreme.com/images/cjtag_diagram.gif
For a slide presentation by Stephen Lau of TI on 1149.7, a complementary superset of the 1149.1 standard, see “Squeezing the Power out of Debug and Test Interface (DTI)” at: http://www.ip-extreme.com/cjtag_preso.pdf
Keywords:
IEEE 1149.7, cJTAG, IEEE 1149.1, JTAG, compact JTAG, test, debug, test and debug, semiconductor IP, IP core, IEEE 1149.1, SoC, system on chip, IC, integrated circuit, embedded systems, multicore devices, mobile devices, power saving
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