Singapore – 26 February 2014 –STATS ChipPAC, a leading provider of advanced semiconductor packaging and test services, announced today that unit shipments of semiconductor packages utilising the Company’s patented fcCuBE® technology more than quadrupled in 2013 compared to 2012. The performance and cost advantages of this advanced flip chip packaging technology has driven adoption by customers in the mobile, consumer and cloud computing markets.
The most significant area of growth and adoption of fcCuBE technology to date has been in application processors, baseband processors, power management and connectivity integrated circuits (ICs) for the low to high-end mobile market as well as global positioning systems (GPS) and set top box chipsets in the consumer market. Key building blocks of this innovative flip chip technology, namely copper (Cu) column bumps and Bond-on-Lead (BOL) design and interconnection, have delivered clear advantages to customers by providing a higher routing density at a lower cost.
“With the ever increasing demand for sophisticated devices with faster processing speeds and higher input/output (I/O) in the smallest footprint possible, fcCuBE delivers a lower cost flip chip package with enhanced reliability across a wide range of configurations. The scalability of fcCuBE to support customers with progressively finer bump pitches and increasing I/O densities for advanced silicon (Si) nodes at a lower cost has been a key factor in the significant increase we have seen in our design wins. We provide customers with a strong competitive advantage in markets where the performance and cost advantages of flip chip interconnect may not have been feasible before,” said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC.
The advantages of fcCuBE are driving wider customer adoption from cost sensitive markets such as mobile and consumer to networking and cloud computing where increased routing density and performance are imperative. fcCuBE’s unique BOL interconnect structure provides scalability to very fine bump pitches and high I/O while alleviating stress-related chip to package interaction (CPI), a common phenomenon associated with lead free and copper column bump structures. This is particularly important for mid- to high-end networking and consumer applications such as Ethernet processor, graphics processing units (GPUs), network storage ICs, memory controllers and digital television (DTV) ICs.
An important feature of fcCuBE technology is the inherent compatibility of the basic design with both mass reflow (MR) and Thermo-Compression Bonding (TCB) processes. STATS ChipPAC’s uniquely developed MR process supports bump pitches down to 80um and below, providing customers a lower cost alternative to TCB at these pitches. TCB is utilised for more complex face-to-back or face-to-face bonding of processes necessitated by Through Silicon Via (TSV) technology.
Dr. Raj Pendse, STATS ChipPAC’s Vice President and Chief Marketing Officer noted, “The attributes of fcCuBE® technology offer our customers a scalable path for first level interconnection of new Si nodes. Furthermore, fcCuBE® complements our other flagship technologies such as fan-out wafer level packaging, providing customers the optimum solution across the full spectrum of IC designs and end applications.”