The Elastix product line will read in a Verilog netlist, for which it uses the Verific Netlist Only Parser, and is built on top of Verific’s netlist data structures. Verific’s Netlist Only Parser includes a complete set of routines to traverse and manipulate stored netlists and is widely regarded as an excellent foundation for any netlist-oriented electronic design automation (EDA) application.
“I am pleased with Verific’s software,” says Emre Tuncer, vice president of engineering of Elastix. “Using the netlist parser and data structures enabled us to kick-start our development and focus on our core technology early on. It is well structured, easy to understand and efficient.”
Adds Michiel Ligthart, Verific’s chief operating officer: “Startups such as Elastix well understand the need to stay focused on their core competencies which is why they turn to Verific for proven datastructures and netlist parsers.”
The Verific product portfolio includes Verilog, SystemVerilog and VHDL parsers, analyzers and elaborators, as well as a netlist-oriented database. Verific’s software serves as the front end to the most popular EDA tools for analyzing, verifying, synthesizing and modifying designs. Its products are written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. Each is licensed as source code and comes with support and maintenance.
About Elastix Corporation
Elastix is developing software solutions to minimize power consumption using variability-aware techniques. Elastix solutions fit in traditional EDA and signoff flows, and deliver IC designs with lower worst-case power and lower average power consumption when compared to traditional IC designs. Elastix has offices in Barcelona, Spain, and Los Gatos, Calif. Elastix’s Spain offices are located at: Sant Joan de La Salle 42, Fourth Floor, 08022 Barcelona, Spain. U.S. offices are located at: 420 Blossom Hill Road, Suite 101, Los Gatos, Calif. 95032. For more information, send email to Email Contact. Website: www.elastix-corp.com.
About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, is a leading provider of Verilog and VHDL front-end software founded in 1999 by EDA industry veteran Rob Dekker. Verific’s software is used worldwide in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website: www.verific.com.
Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
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Public Relations for Verific
Nanette Collins, 617-437-1822
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