The ATE and EDA member companies plan to implement tools to support this standard. Semiconductor manufacturers are encouraged to work with their EDA and ATE partner companies to evaluate and adapt the new data-logging format in their flows to get the benefits of the new standard.
Interested parties are invited to attend a tutorial on the STDF fail datalog standard at the International Test Conference (ITC) in an Advanced Industrial Practices (AIP) session from 8:30-10 am on Thursday, Oct. 30. Group members, Ajay Khoche and Phil Burlison of Verigy, John Rowe of Teradyne and Glenn Plowman of Qualcomm will present.
Verigy has developed STDF Navigator, a software tool to assist users in adopting the new standard. The tool automatically validates the readers and writers for conformance to the new standard. This tool will be available beginning Monday, Nov. 3, free of charge through the group’s Web site or by contacting the group’s chairman, Ajay Khoche, directly.
In addition, the memory fail datalog subgroup has completed the first draft of the STDF fail datalog standard for embedded and standalone memories. This draft standard will follow the same review and ballot process as the scan fail datalog, and is expected to be completed by mid-2009.
The Group was initiated by Verigy at SEMICON West in July 2006 to address an emerging bottleneck in the collecting and analyzing of structural fail information in volume production. Recognizing that a widely-adopted, efficient standard format for storing and exchanging the structural fail data between test and design for yield analysis is imperative for yield improvements at 65nm and beyond and will only become more important at each smaller processing node, the group has been collaborating on the definition of this new standard specification.
“The productive collaboration of this group demonstrates our collective understanding of the unique interdependencies between each aspect of the chip development process and the significance of the need for this new standard,” said Group chairman, Ajay Khoche, who is Verigy's EDA/DFT alliance manager. “As a result of our cooperative efforts, we were able to develop the standard which will lead the way to a streamlined flow for faster time-to-yield.”
STDF Fail Data Standardization Group Participating Companies
The STDF Data Logging Standards Development Group is organized in two working groups to address the unique data logging requirements for logic and memory devices.
|
Logic Device Working Group Members: |
| Chair: Ajay Khoche, Verigy |
| Vice-Chair: Andreas Leininger, Infineon Technologies, AG |
| Participating Companies: |
| Advantest Corp. |
| Nano Integrated Solutions Inc. |
| Cadence Design Systems, Inc. |
| Freescale Semiconductor |
| IBM |
| Infineon Technologies, AG |
| LTX/Credence |
| LogicVision |
| Mentor Graphics Corp. |
| Open Source Consortium |
| QUALCOMM Inc. |
| Soto Technology |
| STMicroelectronics |
| Synopsys, Inc. |
| Teradyne, Inc. |
| Texas Instruments, Inc. |
| Verigy |
| Yield Dynamics Inc. (Now Part of MKS Instruments) |
|
Memory Device Working Group Members: |
| Chair: Ajay Khoche, Verigy |
| Co-Vice-Chairs: Sauro Landini, ARM; Liyang Lai, Mentor Graphics Corp. |
| Participating Companies: |
| ARM |
| Freescale Semiconductor |
| Mentor Graphics Corp. |
| PDF Solutions, Inc. |
| QUALCOMM Inc. |
| Teradyne, Inc. |
| Verigy |
| Virage Logic Corp. |
| Yield Dynamics, Inc. (Now Part of MKS Instruments) |
STDF Fail Data Standardization Group
The STDF Fail Data Standardization Group is an informal industry standards working group made up of representatives from automatic test equipment (ATE) suppliers, electronic design automation (EDA) tool vendors and leading semiconductor manufacturers to collaborate on a standard data format for sharing of structural fail information for yield analysis. The standard will benefit anyone who uses semiconductor test results and all interested parties are welcome to join the group. Interested industry members who would like to participate in establishing this standard are invited to contact Ajay Khoche at +1 408.864.5123 or Email Contact. More information is available at http://stdf.bcsweb.com.
Contact:
Verigy
Jana Knezovich, +1-408-864-5987
Email Contact