WHO:
Jasper Design Automation, the leader in successful deployment of production proven formal verification solutions, today announced its plans to provide a limited number of demo suite demonstrations of its Formal Verification Unleashed™ - an advanced verification methodology supported by best-in-class formal verification solutions, to exhaustively verify complex designs at any stage in the design flow, from architecture-level down to first silicon.
WHAT:
The Demo Suite Booking Calendar is now open and can be found at www.jasper-da.com. Book your appointment today to ensure a time slot for you and your team with the formal verification experts at Jasper Design Automation. Learn how industry-leading companies worldwide have applied high-capacity, high-performance formal verification solutions from Jasper Design Automation to successfully prove protocols and executable specs, to design, explore and debug RTL, to ensure correctness of block-level functionality and to conduct fast and exhaustive post-silicon debug. Private appointments in Jasper’s Demo Suites may be booked in advance by visiting http://www.jasper-da.com, emailing Email Contact, or by calling +1.650.966.0245.
Floor demonstrations of the newest releases of JasperGold® Verification System, and GamePlan™ Verification Planner will also be available during exhibit hours in Jasper’s booth, #2346.
WHEN:
June 8th-12th, 9:00am to 5:00pm; June 13th, 9:00am to 12:00pm
WHERE:
Booth #2346, Anaheim Convention Center, Anaheim, California
About Jasper Design Automation
Jasper Design Automation’s production proven formal verification solutions are used by logic designers, verification engineers and silicon bring-up teams to design, explore and debug RTL, to ensure correctness of block-level functionality and for rapid post-silicon validation and debug. JasperGold® Verification System delivers complete “deep formal” systematic verification, ensuring correctness of critical design features without any testbench development. JasperGold Express, a “light formal” solution, complements simulation by accelerating bug-hunting and coverage attainment. For expert help with large scale formal verification deployment, RTL exploration or post-silicon debug, please visit http://www.jasper-da.com.
Jasper Design Automation, the Jasper Design Automation logo, JasperGold, Formal Testplanner, GamePlan, Proof Accelerators, Lossless Abstractions, Formal Scoreboard, and Design Tunneling are trademarks or registered trademarks of Jasper Design Automation, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.
Contact:
For Jasper Design Automation
Francine Bacchini, +1-408-839-8153
Email Contact